Patents by Inventor Hadi Jebory
Hadi Jebory has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180247822Abstract: A semiconductor wafer having a plurality of through substrate vias (TSVs) is disclosed. The semiconductor wafer includes a stepped support ring on an outer edge of the semiconductor wafer, a usable back side region of the semiconductor wafer substantially enclosed by the stepped support ring, and the plurality of TSVs extending from a front side of the semiconductor wafer to the usable back side region of the semiconductor wafer. The stepped support ring includes a step between an outer ring and an inner ring of the stepped support ring. The semiconductor wafer further includes a back side metal on the usable back side region of the semiconductor wafer, a plurality of semiconductor devices on the front side of the semiconductor wafer, where at least one of the plurality of semiconductor devices is coupled to the back side metal through at least one of the plurality of TSVs.Type: ApplicationFiled: April 30, 2018Publication date: August 30, 2018Inventors: David J. Howard, Hadi Jebory
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Patent number: 9984888Abstract: A semiconductor wafer having a plurality of through substrate vias (TSVs) is disclosed. The semiconductor wafer includes a stepped support ring on an outer edge of the semiconductor wafer, a usable back side region of the semiconductor wafer substantially enclosed by the stepped support ring, and the plurality of TSVs extending from a front side of the semiconductor wafer to the usable back side region of the semiconductor wafer. The stepped support ring includes a step between an outer ring and an inner ring of the stepped support ring. The semiconductor wafer further includes a back side metal on the usable back side region of the semiconductor wafer, a plurality of semiconductor devices on the front side of the semiconductor wafer, where at least one of the plurality of semiconductor devices is coupled to the back side metal through at least one of the plurality of TSVs.Type: GrantFiled: July 8, 2015Date of Patent: May 29, 2018Assignee: Newport Fab, LLCInventors: David J. Howard, Hadi Jebory
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Patent number: 9673081Abstract: Disclosed are a structure for improving electrical signal isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench having sidewalls disposed in the semiconductor substrate. An isolation region may be formed along at least an upper portion of the sidewalls of the deep trench, and a metallic filler may be disposed in the deep trench. The isolation region may include a PN junction formed by one or more of ion implantation and annealing, deposition of highly doped polysilicon and out diffusion, and gas phase doping and annealing. In the alternative, the isolation region may be a dielectric isolation region formed by one or more of uniform dielectric deposition, partial dieletric deposition, and dielectric deposition by ionic reaction.Type: GrantFiled: May 1, 2013Date of Patent: June 6, 2017Assignee: Newport Fab, LLCInventors: Hadi Jebory, David J. Howard, Marco Racanelli, Edward Preisler
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Patent number: 9577035Abstract: Disclosed are a structure for providing electrical isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench isolation loop having a first depth disposed in the semiconductor substrate. A dielectric material is disposed in the deep trench isolation loop and one or more through silicon vias (TSVs), having a second depth, are disposed in the semiconductor substrate and within a perimeter of the deep trench isolation loop. A portion of the semiconductor substrate surrounding the deep trench isolation loop may be doped. A metallic filler may be disposed within the one or more TSVs and the metallic filler may be in direct electrical contact with the semiconductor substrate.Type: GrantFiled: July 24, 2013Date of Patent: February 21, 2017Assignee: Newport Fab, LLCInventors: Paul D. Hurwitz, Edward Preisler, Hadi Jebory
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Publication number: 20160379926Abstract: A method of fabricating a semiconductor structure includes: grinding a backside surface of a semiconductor substrate such that the backside surface has a relatively high average roughness (Ra) (when compared with a backside surface subjected to chemical mechanical polishing (CMP)), and then, forming a backside metal structure on the backside surface while the backside surface has the relatively high average roughness. The backside surface can have an average roughness in the range of about 5 to 100 nanometers (or alternately, in the range of about 20 to 40 nanometers) when the backside metal structure is formed. The backside metal structure may be electrically coupled to through silicon vias (TSVs), which supply ground to semiconductor devices fabricated on a front side of the semiconductor substrate.Type: ApplicationFiled: June 22, 2016Publication date: December 29, 2016Inventors: David J. Howard, Hadi Jebory, Marco Racanelli
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Publication number: 20160049355Abstract: A semiconductor wafer having a plurality of through substrate vias (TSVs) is disclosed. The semiconductor wafer includes a stepped support ring on an outer edge of the semiconductor wafer, a usable back side region of the semiconductor wafer substantially enclosed by the stepped support ring, and the plurality of TSVs extending from a front side of the semiconductor wafer to the usable back side region of the semiconductor wafer. The stepped support ring includes a step between an outer ring and an inner ring of the stepped support ring. The semiconductor wafer further includes a back side metal on the usable back side region of the semiconductor wafer, a plurality of semiconductor devices on the front side of the semiconductor wafer, where at least one of the plurality of semiconductor devices is coupled to the back side metal through at least one of the plurality of TSVs.Type: ApplicationFiled: July 8, 2015Publication date: February 18, 2016Inventors: David J. Howard, Hadi Jebory
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Patent number: 9245826Abstract: Disclosed is a structure having anchor vias for improved backside metal adhesion and an associated method for the structure's fabrication. The structure includes at least one anchor via disposed in at least one corner of a semiconductor substrate. A metal filler may be formed within the at least one anchor via, the metal filler having a protruding portion extending from a backside of the semiconductor substrate. The structure may further include a backside metal layer on a bottom surface of the semiconductor substrate, the backside metal layer being bonded to the protruding portion of the metal filler in the at least one anchor via. The at least one anchor via may include a cluster of anchor vias, a plurality of anchor vias disposed in a straight line and/or in a staggered configuration along a periphery of the semiconductor substrate.Type: GrantFiled: January 27, 2014Date of Patent: January 26, 2016Assignee: Newport Fab, LLCInventors: Hadi Jebory, David J. Howard, Scott B. Stetson
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Patent number: 9147609Abstract: Various implementations of through silicon vias with pinched off regions are disclosed. A semiconductor substrate includes a plurality of the through silicon vias disposed in the substrate and extending from a top surface of the substrate to a bottom surface of the substrate. A conductive filler is disposed within each of the plurality of through silicon vias, each of the plurality of through silicon vias having a hollow center which reduces thermal stress in the semiconductor substrate. The plurality of through silicon vias also have pinched off regions at the bottom and/or the top portions of the through silicon vias, which prevent contamination during processing of the semiconductor substrate.Type: GrantFiled: March 8, 2012Date of Patent: September 29, 2015Assignee: Newport Fab, LLCInventors: Hadi Jebory, David J. Howard
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Publication number: 20140252651Abstract: Disclosed is a structure having anchor vias for improved backside metal adhesion and an associated method for the structure's fabrication. The structure includes at least one anchor via disposed in at least one corner of a semiconductor substrate. A metal filler may be formed within the at least one anchor via, the metal filler having a protruding portion extending from a backside of the semiconductor substrate. The structure may further include a backside metal layer on a bottom surface of the semiconductor substrate, the backside metal layer being bonded to the protruding portion of the metal filler in the at least one anchor via. The at least one anchor via may include a cluster of anchor vias, a plurality of anchor vias disposed in a straight line and/or in a staggered configuration along a periphery of the semiconductor substrate.Type: ApplicationFiled: January 27, 2014Publication date: September 11, 2014Applicant: Newport Fab, LLC dba Jazz SemiconductorInventors: Hadi Jebory, David J. Howard, Scott B. Stetson
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Publication number: 20140054743Abstract: Disclosed are a structure for providing electrical isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench isolation loop having a first depth disposed in the semiconductor substrate. A dielectric material is disposed in the deep trench isolation loop and one or more through silicon vias (TSVs), having a second depth, are disposed in the semiconductor substrate and within a perimeter of the deep trench isolation loop. A portion of the semiconductor substrate surrounding the deep trench isolation loop may be doped. A metallic filler may be disposed within the one or more TSVs and the metallic filler may be in direct electrical contact with the semiconductor substrate.Type: ApplicationFiled: July 24, 2013Publication date: February 27, 2014Applicant: Newport Fab, LLC dba Jazz SemiconductorInventors: Paul D. Hurwitz, Edward Preisler, Hadi Jebory
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Publication number: 20130313682Abstract: Disclosed are a structure for improving electrical signal isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench having sidewalls disposed in the semiconductor substrate. An isolation region may be formed along at least an upper portion of the sidewalls of the deep trench, and a metallic filler may be disposed in the deep trench. The isolation region may include a PN junction formed by one or more of ion implantation and annealing, deposition of highly doped polysilicon and out diffusion, and gas phase doping and annealing. In the alternative, the isolation region may be a dielectric isolation region formed by one or more of uniform dielectric deposition, partial dieletric deposition, and dielectric deposition by ionic reaction.Type: ApplicationFiled: May 1, 2013Publication date: November 28, 2013Applicant: Newport Fab, LLC dba Jazz SemiconductorInventors: Hadi Jebory, David J. Howard, Marco Racanelli, Edward Preisler
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Publication number: 20130087893Abstract: Various implementations of through silicon vias with pinched off regions are disclosed. A semiconductor substrate includes a plurality of the through silicon vias disposed in the substrate and extending from a top surface of the substrate to a bottom surface of the substrate. A conductive filler is disposed within each of the plurality of through silicon vias, each of the plurality of through silicon vias having a hollow center which reduces thermal stress in the semiconductor substrate. The plurality of through silicon vias also have pinched off regions at the bottom and/or the top portions of the through silicon vias, which prevent contamination during processing of the semiconductor substrate.Type: ApplicationFiled: March 8, 2012Publication date: April 11, 2013Applicant: NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTORInventors: Hadi Jebory, David J. Howard