Abstract: A method for generating a trained model is provided. The method for generating a trained model includes: receiving a learning data; generating an asymmetric multi-task feature network including a parameter matrix of the trained model which permits an asymmetric knowledge transfer between tasks and a feedback matrix for a feedback connection from the tasks to features; computing a parameter matrix of the asymmetric multi-task feature network using the input learning data to minimize a predetermined objective function; and generating an asymmetric multi-task feature trained model using the computed parameter matrix as the parameter of the generated asymmetric multi-task feature network.

Abstract: A method for generating a trained model is provided. The method for generating a trained model includes: receiving a learning data; generating an asymmetric multi-task feature network including a parameter matrix of the trained model which permits an asymmetric knowledge transfer between tasks and a feedback matrix for a feedback connection from the tasks to features; computing a parameter matrix of the asymmetric multi-task feature network using the input learning data to minimize a predetermined objective function; and generating an asymmetric multi-task feature trained model using the computed parameter matrix as the parameter of the generated asymmetric multi-task feature network.

Abstract: Provided is a flash memory device that can include a memory cell configured to store data, a local bit line that is connected to the memory cell, a global bit line that is connected to the local bit line, a discharge transistor that is connected to the global bit line, and that is configured to selectively connect the global bit line to a reference level responsive to a discharge control signal, and a discharge control circuit, that is connected to the discharge transistor via the discharge control signal, and that is configured to selectively disable the discharge transistor during an erase interval occurring before a verify interval of an erase verification operation carried out by the flash memory device.

Abstract: Provided is a flash memory device that can include a memory cell configured to store data, a local bit line that is connected to the memory cell, a global bit line that is connected to the local bit line, a discharge transistor that is connected to the global bit line, and that is configured to selectively connect the global bit line to a reference level responsive to a discharge control signal, and a discharge control circuit, that is connected to the discharge transistor via the discharge control signal, and that is configured to selectively disable the discharge transistor during an erase interval occurring before a verify interval of an erase verification operation carried out by the flash memory device.