Patents by Inventor Haegeon JUNG
Haegeon JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352527Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.Type: ApplicationFiled: July 7, 2023Publication date: November 2, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Jongsoon PARK, Jongchul Park, Bokyoung Lee, Jeongyun Lee, Hyunggoo Lee, Yeondo Jung, Haegeon Jung
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Patent number: 11735627Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.Type: GrantFiled: May 19, 2021Date of Patent: August 22, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jongsoon Park, Jongchul Park, Bokyoung Lee, Jeongyun Lee, Hyunggoo Lee, Yeondo Jung, Haegeon Jung
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Publication number: 20220189970Abstract: A semiconductor device includes a substrate having a first memory cell and a second memory cell, the first and second memory cells being adjacent to each other in a first direction, first to fourth memory fins adjacent to each other in the first direction in the first memory cell, the first to fourth memory fins protruding from the substrate, fifth to eighth memory fins adjacent to each other in the first direction in the second memory cell, the fifth to eighth memory fins protruding from the substrate, and a first shallow device isolation layer between the fourth memory fin and the fifth memory fin, a sidewall of the first shallow device isolation layer having an inflection point.Type: ApplicationFiled: August 3, 2021Publication date: June 16, 2022Inventors: Haegeon JUNG, Taeyong KWON, Kwang-Yong YANG, Youngmook OH, Bokyoung LEE, Seung Mo HA, Hyunggoo LEE
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Publication number: 20220102493Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch.. The first distance may be about 0.8 times to about 1.2 times the first pitch.Type: ApplicationFiled: May 19, 2021Publication date: March 31, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jongsoon PARK, Jongchul PARK, Bokyoung LEE, Jeongyun LEE, Hyunggoo LEE, Yeondo JUNG, Haegeon JUNG
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Patent number: 10593596Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.Type: GrantFiled: April 23, 2018Date of Patent: March 17, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Dongwoo Han, Kwang-Yong Yang, Jinwook Lee, Kyungyub Jeon, Haegeon Jung, Dohyoung Kim
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Publication number: 20180240710Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.Type: ApplicationFiled: April 23, 2018Publication date: August 23, 2018Inventors: DONGWOO HAN, KWANG-YONG YANG, JINWOOK LEE, KYUNGYUB JEON, HAEGEON JUNG, DOHYOUNG KIM
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Patent number: 9984931Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.Type: GrantFiled: September 9, 2016Date of Patent: May 29, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Dongwoo Han, Kwang-Yong Yang, Jinwook Lee, Kyungyub Jeon, Haegeon Jung, Dohyoung Kim
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Patent number: 9899497Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a āUā-shaped section; and forming source/drain regions in the recess regions.Type: GrantFiled: November 18, 2016Date of Patent: February 20, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin Bum Kim, Kang Hun Moon, Choeun Lee, Kyung Yub Jeon, Sujin Jung, Haegeon Jung, Yang Xu
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Publication number: 20170162674Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a āUā-shaped section; and forming source/drain regions in the recess regions.Type: ApplicationFiled: November 18, 2016Publication date: June 8, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin Bum KIM, Kang Hun MOON, Choeun LEE, Kyung Yub JEON, Sujin JUNG, Haegeon JUNG, Yang XU
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Publication number: 20170084493Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.Type: ApplicationFiled: September 9, 2016Publication date: March 23, 2017Inventors: DONGWOO HAN, KWANG-YONG YANG, JINWOOK LEE, KYUNGYUB JEON, HAEGEON JUNG, DOHYOUNG KIM
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Patent number: 9312181Abstract: The disclosure provides semiconductor devices and methods of manufacturing the same. The method includes etching a substrate using a first mask pattern formed on the substrate to form a trench, forming a preliminary device isolation pattern filling the trench and including first and second regions having first thicknesses, forming a second mask pattern on the first region, etching an upper portion of the second region and a portion of the first mask pattern, which are exposed by the second mask pattern, to form a second region having a second thickness smaller than the first thickness, removing the first and second mask patterns, and etching upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns. An electronic device including a semiconductor device and a manufacturing method thereof are also disclosed.Type: GrantFiled: November 3, 2014Date of Patent: April 12, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Joon Choi, Myeongcheol Kim, Cheol Kim, GeumJung Seong, Hak-Sun Lee, Haegeon Jung, Ji-Eun Han
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Publication number: 20150162247Abstract: The disclosure provides semiconductor devices and methods of manufacturing the same. The method includes etching a substrate using a first mask pattern formed on the substrate to form a trench, forming a preliminary device isolation pattern filling the trench and including first and second regions having first thicknesses, forming a second mask pattern on the first region, etching an upper portion of the second region and a portion of the first mask pattern, which are exposed by the second mask pattern, to form a second region having a second thickness smaller than the first thickness, removing the first and second mask patterns, and etching upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns. An electronic device including a semiconductor device and a manufacturing method thereof are also disclosed.Type: ApplicationFiled: November 3, 2014Publication date: June 11, 2015Inventors: Yong-Joon CHOI, MYEONGCHEOL KIM, CHEOL KIM, GeumJung SEONG, Hak-Sun LEE, Haegeon JUNG, Ji-Eun HAN