Patents by Inventor Hae-Jeong Sohn
Hae-Jeong Sohn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7825523Abstract: A semiconductor package includes a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern, The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region.Type: GrantFiled: December 27, 2006Date of Patent: November 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Patent number: 7576440Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.Type: GrantFiled: November 2, 2006Date of Patent: August 18, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Patent number: 7547977Abstract: In one embodiment, a semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern formed on at least a part of the peripheral region of the semiconductor substrate; a passivation layer formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.Type: GrantFiled: December 27, 2006Date of Patent: June 16, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Patent number: 7541682Abstract: A semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on at least a part of the peripheral region of the semiconductor substrate. A passivation layer is formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.Type: GrantFiled: November 2, 2006Date of Patent: June 2, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Patent number: 7453159Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.Type: GrantFiled: December 27, 2006Date of Patent: November 18, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Publication number: 20070108633Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.Type: ApplicationFiled: December 27, 2006Publication date: May 17, 2007Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Publication number: 20070108562Abstract: A semiconductor package includes a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern, The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region.Type: ApplicationFiled: December 27, 2006Publication date: May 17, 2007Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Hee SONG, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Publication number: 20070108632Abstract: In one embodiment, a semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern formed on at least a part of the peripheral region of the semiconductor substrate; a passivation layer formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.Type: ApplicationFiled: December 27, 2006Publication date: May 17, 2007Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Hee SONG, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Publication number: 20070057383Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.Type: ApplicationFiled: November 2, 2006Publication date: March 15, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Hee SONG, Il-Heung CHOI, Jeong-Jin KIM, Hae-Jeong SOHN, Chung-Woo LEE
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Publication number: 20070057367Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.Type: ApplicationFiled: November 2, 2006Publication date: March 15, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Hee SONG, Il-Heung CHOI, Jeong-Jin KIM, Hae-Jeong SOHN, Chung-Woo LEE
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Patent number: 7148578Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.Type: GrantFiled: August 28, 2003Date of Patent: December 12, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Publication number: 20040041258Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.Type: ApplicationFiled: August 28, 2003Publication date: March 4, 2004Applicant: Samsung Electronic Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Patent number: 6642627Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.Type: GrantFiled: July 9, 2002Date of Patent: November 4, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Publication number: 20030011068Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.Type: ApplicationFiled: July 9, 2002Publication date: January 16, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee