Patents by Inventor Hae-Jin Song
Hae-Jin Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7574638Abstract: The present invention provides semiconductor devices capable of being tested using one test pin and using an input/output pin without any test pins, and methods of testing the same. One semiconductor device comprises a test pin for inputting/outputting test data, an operation mode controller for activating an enable signal in response to an external reset signal and a clock signal, an operation mode storage for receiving serial data synchronized with the clock signal through the test pin in response to the enable signal, and an operation mode decoder for generating operation mode selection signals in response to the serial data stored in the operation mode storage.Type: GrantFiled: February 2, 2006Date of Patent: August 11, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hae-Jin Song, Jin-Tae Joo
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Patent number: 7493440Abstract: There is provided a media access controller with a power-save mode. Particularly, the media access controller of the present invention minimizes power loss by disabling clocks applied to all blocks, including CPU, of the media access controller during the power-save mode. The media access controller of the present invention includes: a power-save master for securing stable transmission/reception of data through bus by respective processors contained in the controller; a wake-up timer for noticing that the power-save mode is expired; a power control unit for determining whether to supply a power to a phase-locked loop, and a timing when clocks for the media access controller are applied and disabled; and a locktime register for storing a locktime when an output of the phase-locked loop is settled. Additionally, there is provided a method of efficiently changing the media access controller from the active mode to the power-save mode, and vice versa.Type: GrantFiled: September 22, 2006Date of Patent: February 17, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hae-Jin Song, Kab-Joo Lee, Yong-Mi Lee
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Patent number: 7180336Abstract: In a clock switching apparatus, a corresponding mask clock signal is generated for at least one of first and second clock signals. A mask clock signal has an interval of a predetermined logical level near the switching between the clock signals. Each mask clock signal is synchronized to the first and/or second clock signals. Such an interval in the mask clock signal prevents occurrence of glitches in an output clock signal that is switched between at least one mask clock signal and/or at least one clock signal.Type: GrantFiled: April 19, 2005Date of Patent: February 20, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Mi Lee, Hae-Jin Song
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Publication number: 20070016812Abstract: There is provided a media access controller with a power-save mode. Particularly, the media access controller of the present invention minimizes power loss by disabling clocks applied to all blocks, including CPU, of the media access controller during the power-save mode. The media access controller of the present invention includes: a power-save master for securing stable transmission/reception of data through bus by respective processors contained in the controller; a wake-up timer for noticing that the power-save mode is expired; a power control unit for determining whether to supply a power to a phase-locked loop, and a timing when clocks for the media access controller are applied and disabled; and a locktime register for storing a locktime when an output of the phase-locked loop is settled. Additionally, there is provided a method of efficiently changing the media access controller from the active mode to the power-save mode, and vice versa.Type: ApplicationFiled: September 22, 2006Publication date: January 18, 2007Inventors: Hae-Jin Song, Kab-Joo Lee, Yong-Mi Lee
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Patent number: 7133944Abstract: There is provided a media access controller with a power-save mode. Particularly, the media access controller of the present invention minimizes power loss by disabling clocks applied to all blocks, including CPU, of the media access controller during the power-save mode. The media access controller of the present invention includes: a power-save master for securing stable transmission/reception of data through bus by respective processors contained in the controller; a wake-up timer for noticing that the power-save mode is expired; a power control unit for determining whether to supply a power to a phase-locked loop, and a timing when clocks for the media access controller are applied and disabled; and a locktime register for storing a locktime when an output of the phase-locked loop is settled. Additionally, there is provided a method of efficiently changing the media access controller from the active mode to the power-save mode, and vice versa.Type: GrantFiled: January 14, 2004Date of Patent: November 7, 2006Assignee: Samsung Electronics, Co., Ltd.Inventors: Hae-Jin Song, Kab-Joo Lee, Yong-Mi Lee
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Publication number: 20060184847Abstract: The present invention provides semiconductor devices capable of being tested using one test pin and using an input/output pin without any test pins, and methods of testing the same. One semiconductor device comprises a test pin for inputting/outputting test data, an operation mode controller for activating an enable signal in response to an external reset signal and a clock signal, an operation mode storage for receiving serial data synchronized with the clock signal through the test pin in response to the enable signal, and an operation mode decoder for generating operation mode selection signals in response to the serial data stored in the operation mode storage.Type: ApplicationFiled: February 2, 2006Publication date: August 17, 2006Applicant: Samsung Electronics Co., LTD.Inventors: Hae-Jin Song, Jin-Tae Joo
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Publication number: 20060026330Abstract: A bus arbitration system includes a bus master, a bus arbitration circuit and a clock signal changing circuit. The bus master is configured to enter a power saving mode of operation in response to a disabled first master clock signal. The bus arbitration circuit is configured to issue a bus access grant to the first bus master in response to a request for bus access issued by the first bus master. The clock signal changing circuit is electrically coupled to the first bus master and the bus arbitration circuit. The clock signal changing circuit is configured to generate the disabled first master clock signal in response to the request for bus access. The clock signal changing circuit is further configured to convert the disabled first master clock signal to an enabled first master clock signal in response to the bus access grant.Type: ApplicationFiled: April 19, 2005Publication date: February 2, 2006Inventors: Doo-youll Yi, Hae-jin Song
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Publication number: 20050270073Abstract: In a clock switching apparatus, a corresponding mask clock signal is generated for at least one of first and second clock signals. A mask clock signal has an interval of a predetermined logical level near the switching between the clock signals. Each mask clock signal is synchronized to the first and/or second clock signals. Such an interval in the mask clock signal prevents occurrence of glitches in an output clock signal that is switched between at least one mask clock signal and/or at least one clock signal.Type: ApplicationFiled: April 19, 2005Publication date: December 8, 2005Inventors: Yong-mi Lee, Hae-Jin Song
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Publication number: 20040151149Abstract: There is provided a media access controller with a power-save mode. Particularly, the media access controller of the present invention minimizes power loss by disabling clocks applied to all blocks, including CPU, of the media access controller during the power-save mode. The media access controller of the present invention includes: a power-save master for securing stable transmission/reception of data through bus by respective processors contained in the controller; a wake-up timer for noticing that the power-save mode is expired; a power control unit for determining whether to supply a power to a phase-locked loop, and a timing when clocks for the media access controller are applied and disabled; and a locktime register for storing a locktime when an output of the phase-locked loop is settled. Additionally, there is provided a method of efficiently changing the media access controller from the active mode to the power-save mode, and vice versa.Type: ApplicationFiled: January 14, 2004Publication date: August 5, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Hae-Jin Song, Kab-Jo Lee, Yong-Mi Lee