Abstract: A super-steep switching device is provided. The super-steep switching device may include a substrate, a semiconductor channel on the substrate, a source electrode and a drain electrode, which are disposed on the semiconductor channel and spaced apart from each other, a gate electrode overlapping a portion of the semiconductor channel and not overlapping a remaining portion of the semiconductor channel, and an insulating layer disposed between the gate electrode and the semiconductor channel and covering an entire surface of the semiconductor channel.

Abstract: A super-steep switching device is provided. The super-steep switching device may include a substrate, a semiconductor channel on the substrate, a source electrode and a drain electrode, which are disposed on the semiconductor channel and spaced apart from each other, a gate electrode overlapping a portion of the semiconductor channel and not overlapping a remaining portion of the semiconductor channel, and an insulating layer disposed between the gate electrode and the semiconductor channel and covering an entire surface of the semiconductor channel.

Abstract: A super-steep switching device and an inverter device using the same are disclosed. The super-steep switching device includes a semiconductor channel disposed on a substrate and made of a semiconductor material having impact ionization characteristic; a source electrode and a drain electrode in contact with the semiconductor channel, wherein the source electrode and the drain electrode are disposed on the substrate and are spaced apart from each other; and a gate electrode disposed on the semiconductor channel so as to overlap only a portion of the semiconductor channel, wherein a top surface of the semiconductor channel includes a first area overlapping the gate electrode, and a second area non-overlapping the gate electrode, wherein a ratio of a length of the first area and a length of the second area is in a range of 1:0.1 to 0.4.

Abstract: A negative transconductance device is disclosed. The negative transconductance device includes a first transistor having a P-type semiconductor channel, a second transistor having an N-type semiconductor channel, and a third transistor having an ambipolar semiconductor channel and positioned between the first and second transistors. A first drain electrode of the first transistor is electrically connected to a third source electrode of the third transistor, and a drain electrode of the third transistor is electrically connected to a second source electrode of the second transistor.

Abstract: A negative transconductance device is disclosed. The negative transconductance device includes a first transistor having a P-type semiconductor channel, a second transistor having an N-type semiconductor channel, and a third transistor having an ambipolar semiconductor channel and positioned between the first and second transistors. A first drain electrode of the first transistor is electrically connected to a third source electrode of the third transistor, and a drain electrode of the third transistor is electrically connected to a second source electrode of the second transistor.