Patents by Inventor Hae Ju CHOI

Hae Ju CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250185252
    Abstract: Provided is a ferroelectric structure. The ferroelectric structure includes: a substrate; a lower electrode disposed on the substrate; a ferroelectric layer disposed on the lower electrode including a two-dimensional ferroelectric material; and an upper electrode disposed on the ferroelectric layer, in which a current value of random intensity is obtained for the same voltage being applied.
    Type: Application
    Filed: June 21, 2024
    Publication date: June 5, 2025
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Sung Joo LEE, Yoon Myung LEE, Seong Kweon KANG, Biswajit DAS, Sang Min LEE, Doo Jin HONG, Jae Rok KIM, Hae Ju CHOI, Sung Pyo BAEK, Tae Ho KANG, Cheol Hwa JANG, Jong Min NOH, Na Yeong LEE
  • Publication number: 20250185407
    Abstract: Provided is a method for manufacturing a stack structure. The method for manufacturing a stack structure includes: preparing a substrate; forming a two-dimensional semiconductor material on the substrate; and oxidizing the two-dimensional semiconductor material using oxygen plasma to form a high-k material layer including the high-k material. The stack structure manufactured through the above-described method may be easily applied to a MOS capacitor, a field effect transistor (FET), an impact ionization super-tilt switching device, a dye-sensitized solar cell, an architectural film (particularly, a film used for window coating), and the like.
    Type: Application
    Filed: June 20, 2024
    Publication date: June 5, 2025
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Sung Joo LEE, Tae Ho KANG, Hae Ju CHOI, Jong Wook JEON, Sung Pyo BAEK, Sang Min LEE, Cheol Hwa JANG, Jong Min NOH, Seong Kweon KANG, Na Yeong LEE
  • Patent number: 12211849
    Abstract: A super-steep switching device is provided. The super-steep switching device may include a substrate, a semiconductor channel on the substrate, a source electrode and a drain electrode, which are disposed on the semiconductor channel and spaced apart from each other, a gate electrode overlapping a portion of the semiconductor channel and not overlapping a remaining portion of the semiconductor channel, and an insulating layer disposed between the gate electrode and the semiconductor channel and covering an entire surface of the semiconductor channel.
    Type: Grant
    Filed: March 7, 2024
    Date of Patent: January 28, 2025
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Hae Ju Choi, Tae Ho Kang, Chan Woo Kang, Hyeon Je Son, Jin Hong Park, Sung Joo Lee, Sung Pyo Baek
  • Publication number: 20240213376
    Abstract: A super-steep switching device is provided. The super-steep switching device may include a substrate, a semiconductor channel on the substrate, a source electrode and a drain electrode, which are disposed on the semiconductor channel and spaced apart from each other, a gate electrode overlapping a portion of the semiconductor channel and not overlapping a remaining portion of the semiconductor channel, and an insulating layer disposed between the gate electrode and the semiconductor channel and covering an entire surface of the semiconductor channel.
    Type: Application
    Filed: March 7, 2024
    Publication date: June 27, 2024
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Hae Ju CHOI, Tae Ho KANG, Chan Woo KANG, Hyeon Je SON, Jin Hong PARK, Sung Joo LEE, Sung Pyo BAEK
  • Publication number: 20240096888
    Abstract: A super-steep switching device and an inverter device using the same are disclosed. The super-steep switching device includes a semiconductor channel disposed on a substrate and made of a semiconductor material having impact ionization characteristic; a source electrode and a drain electrode in contact with the semiconductor channel, wherein the source electrode and the drain electrode are disposed on the substrate and are spaced apart from each other; and a gate electrode disposed on the semiconductor channel so as to overlap only a portion of the semiconductor channel, wherein a top surface of the semiconductor channel includes a first area overlapping the gate electrode, and a second area non-overlapping the gate electrode, wherein a ratio of a length of the first area and a length of the second area is in a range of 1:0.1 to 0.4.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 21, 2024
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Hae Ju CHOI, Tae Ho KANG, Chan Woo KANG, Hyeon Je SON, Jin Hong PARK, Sung Joo LEE, Sung Pyo BAEK
  • Patent number: 11605650
    Abstract: A negative transconductance device is disclosed. The negative transconductance device includes a first transistor having a P-type semiconductor channel, a second transistor having an N-type semiconductor channel, and a third transistor having an ambipolar semiconductor channel and positioned between the first and second transistors. A first drain electrode of the first transistor is electrically connected to a third source electrode of the third transistor, and a drain electrode of the third transistor is electrically connected to a second source electrode of the second transistor.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: March 14, 2023
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Sung Joo Lee, Jeong Ho Cho, Jae Ho Jeon, Hyeon Je Son, Hae Ju Choi, Min Je Kim
  • Publication number: 20210143188
    Abstract: A negative transconductance device is disclosed. The negative transconductance device includes a first transistor having a P-type semiconductor channel, a second transistor having an N-type semiconductor channel, and a third transistor having an ambipolar semiconductor channel and positioned between the first and second transistors. A first drain electrode of the first transistor is electrically connected to a third source electrode of the third transistor, and a drain electrode of the third transistor is electrically connected to a second source electrode of the second transistor.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 13, 2021
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Sung Joo LEE, Jeong Ho CHO, Jae Ho JEON, Hyeon Je SON, Hae Ju CHOI, Min Je KIM