Patents by Inventor Hae-Jung Yu
Hae-Jung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11935867Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.Type: GrantFiled: August 10, 2021Date of Patent: March 19, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yanggyoo Jung, Sungeun Kim, Sangmin Yong, Hae-Jung Yu
-
Publication number: 20230245975Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.Type: ApplicationFiled: April 12, 2023Publication date: August 3, 2023Inventors: Hae-Jung YU, Kyung Suk OH
-
Patent number: 11637070Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.Type: GrantFiled: November 30, 2020Date of Patent: April 25, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hae-Jung Yu, Kyung Suk Oh
-
Publication number: 20230063147Abstract: A semiconductor package includes a substrate and a first semiconductor chip on the substrate and having a first sidewall and a second sidewall different from the first sidewall. A second semiconductor chip is on the substrate and is laterally spaced apart from the first semiconductor chip. A molding layer is on the substrate and between the first sidewall of the first semiconductor chip and a sidewall of the second semiconductor chip. The molding layer exposes the second sidewall of the first semiconductor chip.Type: ApplicationFiled: June 29, 2022Publication date: March 2, 2023Applicant: Samsung Electronics Co., Ltd.Inventor: Hae-Jung YU
-
Publication number: 20220328445Abstract: A semiconductor package includes a first semiconductor chip that has a mount region and an overhang region, a substrate disposed on a bottom surface at the mount region of the first semiconductor chip, and a molding layer disposed on the substrate. The molding layer includes a first molding pattern disposed on a bottom surface at the overhang region of the first semiconductor chip and covering a sidewall of the substrate, and a second molding pattern on the first molding pattern and covering a sidewall of the first semiconductor chip.Type: ApplicationFiled: December 30, 2021Publication date: October 13, 2022Inventor: HAE-JUNG YU
-
Publication number: 20220189916Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.Type: ApplicationFiled: August 10, 2021Publication date: June 16, 2022Inventors: YANGGYOO JUNG, Sungeun KIM, SANGMIN YONG, HAE-JUNG YU
-
Publication number: 20220173044Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the secType: ApplicationFiled: February 18, 2022Publication date: June 2, 2022Inventors: YOUNG KUN JEE, HAE-JUNG YU, SANGWON KIM, UN-BYOUNG KANG, JONGHO LEE, DAE-WOO KIM, WONJAE LEE
-
Patent number: 11282792Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the secType: GrantFiled: March 2, 2020Date of Patent: March 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Kun Jee, Hae-Jung Yu, Sangwon Kim, Un-Byoung Kang, Jongho Lee, Dae-Woo Kim, Wonjae Lee
-
Publication number: 20210082824Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Inventors: Hae-Jung YU, Kyung Suk OH
-
Publication number: 20210005553Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the secType: ApplicationFiled: March 2, 2020Publication date: January 7, 2021Inventors: YOUNG KUN JEE, HAE-JUNG YU, SANGWON KIM, UN-BYOUNG KANG, JONGHO LEE, DAE-WOO KIM, WONJAE LEE
-
Patent number: 10854551Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.Type: GrantFiled: October 16, 2018Date of Patent: December 1, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hae-Jung Yu, Kyung Suk Oh
-
Publication number: 20190244905Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.Type: ApplicationFiled: October 16, 2018Publication date: August 8, 2019Inventors: Hae-Jung YU, Kyung Suk OH
-
Patent number: 9245867Abstract: A package-on-package (POP) electronic device may include first and second packaging substrates, a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates, and first and second sealing layers between the first and second packaging substrates. The first and second sealing layers may be respective first and second epoxy sealing layers. Moreover, the second epoxy sealing layer may include a solder flux agent, and the first epoxy sealing layer may have a lower concentration of the solder flux agent than the second epoxy sealing layer.Type: GrantFiled: May 28, 2014Date of Patent: January 26, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Choongbin Yim, Hae-Jung Yu, Taesung Park
-
Patent number: 9245863Abstract: According to example embodiments of inventive concepts, a semiconductor package apparatus includes a first semiconductor package including a first substrate, a first solder resist layer on the first substrate, and a first sealing member that covers and protects the first solder resist layer, and a plurality of solder balls on the first substrate. The plurality of solder balls includes a first solder ball having a first height and a second solder ball having a second height that is different from the first height. The first sealing member includes holes that expose the solder balls.Type: GrantFiled: July 16, 2013Date of Patent: January 26, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hae-jung Yu, Hak-kyoon Byun, Kyung-tae Na, Seung-hun Han, Tae-sung Park, Choong-bin Yim
-
Patent number: 9054228Abstract: Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer.Type: GrantFiled: January 21, 2014Date of Patent: June 9, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Kyoung Choi, Jong-Youn Kim, Sang-Wook Park, Hae-Jung Yu, In-Young Lee, Sang-Uk Han, Ji-Seok Hong
-
Patent number: 8912048Abstract: A method of fabricating a semiconductor device includes attaching a semiconductor substrate to a carrier using a carrier fixing layer, where the semiconductor substrate including a plurality of semiconductor chips. The method further includes forming gaps between adjacent ones of the chips. The gaps may be formed using one or more chemicals or light which act to remove portions of the semiconductor substrate to expose the carrier fixing layer. Additional portions of the carrier fixing layer are then removed to allow for removal of the chips from the carrier.Type: GrantFiled: March 14, 2013Date of Patent: December 16, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Youn Kim, Ji-Hwang Kim, Hae-Jung Yu, Cha-Jea Jo
-
Publication number: 20140299980Abstract: Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer.Type: ApplicationFiled: January 21, 2014Publication date: October 9, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Eun-Kyoung Choi, Jong-Youn Kim, Sang-Wook Park, Hae-Jung Yu, In-Young Lee, Sang-Uk Han, Ji-Seok Hong
-
Publication number: 20140273348Abstract: A package-on-package (POP) electronic device may include first and second packaging substrates, a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates, and first and second sealing layers between the first and second packaging substrates. The first and second sealing layers may be respective first and second epoxy sealing layers. Moreover, the second epoxy sealing layer may include a solder flux agent, and the first epoxy sealing layer may have a lower concentration of the solder flux agent than the second epoxy sealing layer.Type: ApplicationFiled: May 28, 2014Publication date: September 18, 2014Inventors: Choongbin YIM, Hae-Jung YU, Taesung PARK
-
Publication number: 20140239478Abstract: A semiconductor device includes a first semiconductor chip at least partially overlapping a second semiconductor chip. The first semiconductor chip is coupled to a substrate and has a first width, and the second semiconductor chip has a second width. The device also includes a heat sink coupled to the second semiconductor chip and having a third width different from at least one of the first width or the second width. A package molding section at least partially overlaps a first area of the heat sink and does not overlap a second area of the heat sink which includes a top surface of the heat sink.Type: ApplicationFiled: March 14, 2013Publication date: August 28, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Seok HONG, Sang-Uk HAN, Eun-Kyoung CHOI, Jong-Youn KIM, Hae-Jung YU, Cha-Jea JO
-
Publication number: 20140213017Abstract: A method of fabricating a semiconductor device includes attaching a semiconductor substrate to a carrier using a carrier fixing layer, where the semiconductor substrate including a plurality of semiconductor chips. The method further includes forming gaps between adjacent ones of the chips. The gaps may be formed using one or more chemicals or light which act to remove portions of the semiconductor substrate to expose the carrier fixing layer. Additional portions of the carrier fixing layer are then removed to allow for removal of the chips from the carrier.Type: ApplicationFiled: March 14, 2013Publication date: July 31, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Youn KIM, Ji-Hwang KIM, Hae-Jung YU, Cha-Jea JO