Abstract: A functional food composition contains a Lonicera japonica extract as an active ingredient is disclosed. The functional food composition is useful in alleviating irritable bowel syndrome. The Lonicera japonica extract reduces diarrhea and/or intestinal intonation symptoms, thereby exhibiting an effect of alleviating irritable bowel syndrome. A method of treating or alleviating irritable bowel syndrome includes a step of administering a composition to a subject, wherein the composition contains a Lonicera japonica extract.

Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the sec

Abstract: A method of predicting a life of a membrane electrode assembly (MEA) of a fuel cell for electric power generation includes: deriving an operating condition for accelerated degradation, which is applicable to the fuel cell; operating the fuel cell for a specific time under the derived operating condition for accelerated degradation and under a normal operating condition, and identifying the degree of degradation of the fuel cell under each of the operating conditions; calculating an acceleration multiple based on the degree of degradation identified under the operating condition for accelerated degradation and under the normal operating condition; and predicting the life of the membrane electrode assembly based on the acceleration multiple.

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the sec

Abstract: A semiconductor device including: a semiconductor substrate including an active region; a plurality of conductive structures formed over the semiconductor substrate; an isolation layer filling a space between the conductive structures and having an opening that exposes the active region between the conductive structures; a pad formed in a bottom portion of the opening and in contact with the active region; a plug liner formed conformally over a sidewall of the opening and exposing the pad; and a contact plug formed over the pad inside the opening.

Abstract: A self-healing conjugated polymer is disclosed. The self-healing conjugated polymer has hydrogen bonding functional groups introduced into its side chains. Due to this structure, the conjugated polymer is imparted with the ability to recover through self-healing while maintaining its inherent properties (for example, physical and electrical properties). Based on this effective self-healing ability, the conjugated polymer is expected to find application as a biomaterial, a pharmaceutical material, a nonlinear optical material or an organic electronic material.

Abstract: A fuel cell system includes a fuel cell stack including fuel and air electrodes, a fuel gas supply module configured to supply hydrogen and oxygen, as fuel gases, to the fuel cell stack, a fuel gas supply line including channels through which the fuel gases are supplied to the fuel cell stack, a humidification module disposed in the fuel gas supply line and configured to supply moisture to the fuel gases, and a controller configured to control the fuel gas supply line such that the fuel gases bypass the humidification module and are directly supplied to the fuel cell stack when temperature of the fuel cell stack is determined low at an initial stage of operation of the fuel cell stack, and the fuel gases pass through the humidification module and are supplied to the fuel cell stack when the temperature reaches a normal temperature.

Abstract: A conjugated polymer that is an electron donor, that is soluble without aggregation, that is solution-coatable and is dryable at a temperature below 70° C., that has an energy conversion efficiency of 7 % or more over an area of 5 cm2 or more, and that is composed of a repeating unit represented by Chemical Formula 1A below: where x is a real number from 0.1 to 0.2; and n is an integer from 1 to 1,000. The conjugated polymer forms a uniform thin film over a large area of, for example, an organic solar cell, without a heat treatment due to superior solubility and crystallinity at low temperature and, thus, allows fabrication of an organic solar cell with high efficiency at a low temperature.

Abstract: The present disclosure relates to a conjugated polymer and a perovskite solar cell including the same, more particularly to a conjugated polymer capable of improving moisture stability and thermal stability. When the conjugated polymer according to the present disclosure is used in an organic electronic device, superior efficiency can be maintained for a long period of time.

Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.

Abstract: Provided are a multi-direction channel transistor having a gate having an increased effective width and a multi-direction channel, and a semiconductor device including the multi-direction channel transistor, wherein the multi-direction channel transistor includes at least one fin on an active region on a substrate and disposed adjacent to a recess extending in a first direction; a gate line extending in a second direction crossing the first direction and covering at least a portion of the at least one fin and the recess; source/drain regions on the active region at both sides of the gate line; and a channel region in the active region under the gate line between the source/drain regions, wherein the first direction is diagonal to the second direction, and a dielectric film under the gate line has substantially the same thickness on both the at least one fin and the recess.

Abstract: A method of predicting a life of a membrane electrode assembly (MEA) of a fuel cell for electric power generation includes: deriving an operating condition for accelerated degradation, which is applicable to the fuel cell; operating the fuel cell for a specific time under the derived operating condition for accelerated degradation and under a normal operating condition, and identifying the degree of degradation of the fuel cell under each of the operating conditions; calculating an acceleration multiple based on the degree of degradation identified under the operating condition for accelerated degradation and under the normal operating condition; and predicting the life of the membrane electrode assembly based on the acceleration multiple.

Abstract: An electronic device includes a circuit board including at least one electronic component, a housing accommodating the circuit board, an emissivity control layer disposed in an upper portion of the circuit board and transmitting radiant heat generated by the electronic component, and a temperature controller controlling an amount of the radiant heat transmitted to the housing by adjusting the emissivity of the emissivity control layer. The temperature controller may adjust the emissivity of the emissivity control layer to a first range value, when the electronic device is in an idle state, not performing a foreground operation, and may adjust the emissivity of the emissivity control layer to a second range value, lower than the first range value, when the electronic device is in a busy state, performing the foreground operation.

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the sec

Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.

Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.

Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.

Abstract: Provided are a multi-direction channel transistor having a gate having an increased effective width and a multi-direction channel, and a semiconductor device including the multi-direction channel transistor, wherein the multi-direction channel transistor includes at least one fin on an active region on a substrate and disposed adjacent to a recess extending in a first direction; a gate line extending in a second direction crossing the first direction and covering at least a portion of the at least one fin and the recess; source/drain regions on the active region at both sides of the gate line; and a channel region in the active region under the gate line between the source/drain regions, wherein the first direction is diagonal to the second direction, and a dielectric film under the gate line has substantially the same thickness on both the at least one fin and the recess.

Abstract: The present disclosure relates to a conjugated polymer for a low-temperature process, which is capable of forming a uniform thin film over a large area without a heat treatment process due to superior solubility and crystallinity at low temperature and, thus, allows fabrication of an organic solar cell with high efficiency at low temperature.