Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.

Abstract: A fluorescent protein sensor capable of quantitatively measuring oxidation degree of methionine residues of a specific protein, and a use thereof. Specifically, a fluorescent biosensor recombinant protein in which an MsrB protein, a cpYFP protein, a thioredoxin 3 protein, a linker protein and a G protein are linked in this order, and which is capable of quantitatively measuring the oxidation degree of methionine residues of a target protein; a fluorescent biosensor comprising same; a method for measuring oxidation degree of methionine residues of a target protein; and an information providing method for diagnosis of oxidative stress-associated diseases; and a method for screening for a therapeutic agent for oxidative stress-associated diseases.

Abstract: A method for manufacturing a surge absorbing device is provided. The method includes providing an elongate ceramic tube having a hollow space defined therein and having open and opposite first and second end; forming a first plating layer and a second plating layer on the first end and the second end, respectively; placing a surge absorbing element within the hollow space within the ceramic tube; disposing first and second brazing rings on the first plating layer and the second plating layer, respectively; disposing first and second sealing electrodes on the first and second brazing rings respectively; and melting the first and second brazing rings in an inert gas atmosphere to attach the first and second sealing electrodes onto the first plating layer and the second plating layer, respectively.

Abstract: A semiconductor memory device includes a peripheral logic structure including peripheral circuits on a substrate, a horizontal semiconductor layer extending along a top surface of the peripheral logic structure, a plurality of stack structures arranged on the horizontal semiconductor layer along a first direction, and a plurality of electrode separation regions in each of the plurality of stack structures to extend in a second direction, which is different from the first direction, wherein each of the plurality of stack structures includes a first electrode pad and a second electrode pad on the first electrode pad, the first electrode pad protruding in the first direction beyond the second electrode pad by a first width, and the first electrode pad protrudes in the second direction beyond the second electrode pad by a second width, which is different from the first width.

Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.

Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.

Abstract: A method for manufacturing a surge absorbing device is provided. The method includes providing an elongate ceramic tube having a hollow space defined therein and having open and opposite first and second end; forming a first plating layer and a second plating layer on the first end and the second end, respectively; placing a surge absorbing element within the hollow space within the ceramic tube; disposing first and second brazing rings on the first plating layer and the second plating layer, respectively; disposing first and second sealing electrodes on the first and second brazing rings respectively; and melting the first and second brazing rings in an inert gas atmosphere to attach the first and second sealing electrodes onto the first plating layer and the second plating layer, respectively.

Abstract: A method for manufacturing a surge absorbing device is provided. The method includes providing an elongate ceramic tube having a hollow space defined therein and having open and opposite first and second end; forming a first plating layer and a second plating layer on the first end and the second end, respectively; placing a surge absorbing element within the hollow space within the ceramic tube; disposing first and second brazing rings on the first plating layer and the second plating layer, respectively; disposing first and second sealing electrodes on the first and second brazing rings respectively; and melting the first and second brazing rings in an inert gas atmosphere to attach the first and second sealing electrodes onto the first plating layer and the second plating layer, respectively.

Abstract: A semiconductor memory device includes a peripheral logic structure including peripheral circuits on a substrate, a horizontal semiconductor layer extending along a top surface of the peripheral logic structure, a plurality of stack structures arranged on the horizontal semiconductor layer along a first direction, and a plurality of electrode separation regions in each of the plurality of stack structures to extend in a second direction, which is different from the first direction, wherein each of the plurality of stack structures includes a first electrode pad and a second electrode pad on the first electrode pad, the first electrode pad protruding in the first direction beyond the second electrode pad by a first width, and the first electrode pad protrudes in the second direction beyond the second electrode pad by a second width, which is different from the first width.

Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.

Abstract: A vertical memory device includes a substrate including a first region including a cell array formed thereon and a second region surrounding the first region, the second region including a stair structure formed thereon, gate electrodes stacked on the substrate to be spaced apart from each other in a first direction vertical to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate and including a pad at an end portion thereof in the second direction, a channel extending through the gate electrodes in the first direction on the first region of the substrate, and contact plugs formed on the second region, the contact plugs extending in the first direction to contact the pads of the gate electrodes respectively.

Abstract: A vertical memory device includes a substrate including a first region including a cell array formed thereon and a second region surrounding the first region, the second region including a stair structure formed thereon, gate electrodes stacked on the substrate to be spaced apart from each other in a first direction vertical to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate and including a pad at an end portion thereof in the second direction, a channel extending through the gate electrodes in the first direction on the first region of the substrate, and contact plugs formed on the second region, the contact plugs extending in the first direction to contact the pads of the gate electrodes respectively.

Abstract: There is provided a method for manufacturing a flexible electrode, the method comprising: cleaning a plastic substrate; forming a metal-oxide seed layer on the plastic substrate by sputtering a metal oxide on the plastic substrate; and forming a metal plating layer on the metal oxide seed layer using an electroless plating.

Abstract: The present disclosure provides a method for manufacturing a surge absorbing device, the method comprising: providing an elongate ceramic tube having a hollow space defined therein and having open and opposite first and second end; forming a first plating layer and a second plating layer on the first end and the second end, respectively; placing a surge absorbing element within the hollow space within the ceramic tube; disposing first and second brazing rings on the first plating layer and the second plating layer, respectively; disposing first and second sealing electrodes on the first and second brazing rings respectively; and melting the first and second brazing rings in an inert gas atmosphere to attach the first and second sealing electrodes onto the first plating layer and the second plating layer, respectively.

Abstract: There is provided a method for manufacturing a flexible electrode, the method comprising: cleaning a plastic substrate; forming a metal-oxide seed layer on the plastic substrate by sputtering a metal oxide on the plastic substrate; and forming a metal plating layer on the metal oxide seed layer using an electroless plating.

Abstract: Disclosed is a method of preparing a metal oxide-graphene nanocomposite, including preparing a nanocomposite material, forming graphene flakes by pretreating the nanocomposite material, and hydrothermally synthesizing the pretreated nanocomposite material. A method of manufacturing an electrode using the metal oxide-graphene nanocomposite is also provided. According to this invention, the metal oxide-graphene nanocomposite is synthesized from inexpensive graphite through one-step processing using only a surfactant, in place of conventional methods using oxidants, reductants and high-temperature heat, thereby lowering the number of processing steps and processing costs. Also, in the fabrication of the electrode, low electrical resistance characteristic of graphene is applied as it is, in place of the conventional use of active material, conductive material and binder, thereby exhibiting desired processing efficiency without the addition of the conductive material.