Abstract: An integrated circuit includes a memory cell array coupled to a bitline and a first wordline and a negative-type metal-oxide-semiconductors (NMOS) pull-down structure coupled to the bitline and PMOS transistors. The positive-type metal-oxide-semiconductors (PMOS) transistors may be coupled to a second wordline, where a logic value carried on the second wordline is based on a logic value carried on the first wordline, and the PMOS transistors are structured to pre-charge respective drains of the NMOS pull-down structure to a high logic value based on a low logic value carried on the second wordline. The NMOS pull-down structure may be structured to discharge the bitline based on a high logic value carried on the second wordline.

Abstract: An integrated circuit includes a memory cell array coupled to a bitline and a first wordline and a negative-type metal-oxide-semiconductors (NMOS) pull-down structure coupled to the bitline and PMOS transistors. The positive-type metal-oxide-semiconductors (PMOS) transistors may be coupled to a second wordline, where a logic value carried on the second wordline is based on a logic value carried on the first wordline, and the PMOS transistors are structured to pre-charge respective drains of the NMOS pull-down structure to a high logic value based on a low logic value carried on the second wordline. The NMOS pull-down structure may be structured to discharge the bitline based on a high logic value carried on the second wordline.

Abstract: A dual-port memory including a first memory array and at least one address decoder. The first memory array includes memory cells and two ports for each of the memory cells. The at least one address decoder generates word line signals for concurrent access to two ports of one or more cells of the memory cells in a same row of the first memory array. Each of the word line signals is generated to perform a read operation. Pulse widths of the word line signals for the read operations are proportional to a ratio of (i) a reference amount of cell current of a cell of a reference memory array to (ii) an amount of cell current of the one or more cells of the plurality of memory cells in a same row of the first memory array.

Abstract: Embodiments include a method comprising: receiving a first voltage; and while testing a memory cell: modifying the first voltage to generate a second voltage that is different from the first voltage; and performing a first read operation on the memory cell, based on applying (i) the second voltage to an array of transistors of the memory cell and (ii) the first voltage to the memory cell.

Abstract: Embodiments include a method comprising: receiving a first voltage; and while testing a memory cell: modifying the first voltage to generate a second voltage that is different from the first voltage; and performing a first read operation on the memory cell, based on applying (i) the second voltage to an array of transistors of the memory cell and (ii) the first voltage to the memory cell.

Abstract: An apparatus to test a semiconductor package includes a vertical illuminator to supply vertical illumination in the same axial direction as a measurement target and a vertical image unit to capture a vertical image of the measurement target so that a testing apparatus may 2-dimensionally determine information on the shape, size, or position of a solder ball. An inclined illuminator may supply inclined illumination in a different axial direction from the measurement target, and an inclined image capture unit may capture a side image of the measurement target so that the testing apparatus may 3-dimensionally determine information on a state of contact of the solder ball with the ball land. The inclined image capture unit may include a color camera using color information, thereby markedly increasing test reliability and yield.

Abstract: An apparatus to test a semiconductor package includes a vertical illuminator to supply vertical illumination in the same axial direction as a measurement target and a vertical image unit to capture a vertical image of the measurement target so that a testing apparatus may 2-dimensionally determine information on the shape, size, or position of a solder ball. An inclined illuminator may supply inclined illumination in a different axial direction from the measurement target, and an inclined image capture unit may capture a side image of the measurement target so that the testing apparatus may 3-dimensionally determine information on a state of contact of the solder ball with the ball land. The inclined image capture unit may include a color camera using color information, thereby markedly increasing test reliability and yield.

Abstract: An apparatus to test a semiconductor package includes a vertical illuminator to supply vertical illumination in the same axial direction as a measurement target and a vertical image unit to capture a vertical image of the measurement target so that a testing apparatus may 2-dimensionally determine information on the shape, size, or position of a solder ball. An inclined illuminator may supply inclined illumination in a different axial direction from the measurement target, and an inclined image capture unit may capture a side image of the measurement target so that the testing apparatus may 3-dimensionally determine information on a state of contact of the solder ball with the ball land. The inclined image capture unit may include a color camera using color information, thereby markedly increasing test reliability and yield.

Abstract: A system, method and computer program product are provided for producing an instance of a memory device from a banked memory architecture. The banked memory architecture specifies a maximum number of memory banks and a maximum number of rows per memory bank. The method comprises the step of receiving input parameters indicating a number of properties of the memory device, the properties comprising at least a number of rows R for the memory device. Thereafter, a degeneration process is performed on the banked memory architecture in order to produce the instance of a memory device having those properties.

Abstract: A system, method and computer program product are provided for producing an instance of a memory device from a banked memory architecture. The banked memory architecture specifies a maximum number of memory banks and a maximum number of rows per memory bank. The method comprises the step of receiving input parameters indicating a number of properties of the memory device, the properties comprising at least a number of rows R for the memory device. Thereafter, a degeneration process is performed on the banked memory architecture in order to produce the instance of a memory device having those properties.

Abstract: A memory device is provided comprising a memory array consisting of a plurality of memory cells. These memory cells are accessed via a plurality of word lines and a plurality of bit lines. Multiplexer logic is provided which has the plurality of bit lines connected to its inputs, and is arranged to connect one of those inputs to its output dependent on a multiplexer control signal. Decoder logic is responsive to an address to produce the multiplexer control signal and to select one of the word lines, as a result of which a particular memory cell in the memory array identified by the address has its associated bit line connected to the output of a multiplexer logic. Sense amp logic is coupled to the output of the multiplexer logic and has a precharge node used during a sensing operation to detect a stored data state of the particular memory cell.

Abstract: A composite liquid crystal panel that interacts with an inspection station to simulate operating liquid crystal displays, and methods of fabricating and testing such liquid crystal panels. The composite liquid crystal panel enables the application of operating voltages to a plurality of unit liquid crystal panel areas. The inspection station provides operating power, illuminating light, and first and second polarizers. When power is applied to the composite liquid crystal panel an image is produced. That image will show defects in the unit liquid crystal panel areas. Beneficially, the inspection station tilts to enable easier problem identification.

Abstract: A portable jig for facilitating the transport and storage a liquid crystal syringe includes a supporting die including at least one inspection hole, at least one receiving hole for receiving at least one liquid crystal syringe at an upper portion thereof and having a flange for fixing an upper end portion of the liquid crystal syringe, and an airtight lower face.

Abstract: A liquid crystal display device includes a liquid crystal display panel having a liquid crystal area defined within a display area by a sealant, and a non-display area formed in an outer part of the display area, and at least one bubble trap arranged in the outer part of the sealant within the non-display area and patterned to have a concave surface facing toward outside of the non-display area.

Abstract: Disclosed is a system for fabricating a liquid crystal display using liquid crystal dropping and a method of fabricating a liquid crystal display using the same. The present invention includes a liquid crystal forming line dropping liquid crystals on the first substrate, a sealant forming line forming the sealant on the second substrate, and a bonding and hardening line bonding the two substrates to each other and hardening the sealant, printing a sealant, bonding the substrates each other, and hardening the sealant and an inspection process line of cutting the bonded substrates into panel units and grinding and inspecting the unit panels.

Abstract: An apparatus for fabricating a flat panel display device includes a substrate on which a picture display section is formed and a stage on which the substrate is loaded. A dispenser applies a sealant along an outer line of the picture display section in the substrate. A light detector emits light toward the sealant and detects the amount of reflected light in real-time. A controller detects broken lines in the sealant in accordance with a signal supplied from the light detector and controls the dispenser so as to re-apply the sealant to spaces in the broken line in which the sealant is not present.

Abstract: Disclosed is a system for fabricating a liquid crystal display using liquid crystal dropping and a method of fabricating a liquid crystal display using the same. The present invention includes a liquid crystal forming line dropping liquid crystals on the first substrate, a sealant forming line forming the sealant on the second substrate, and a bonding and hardening line bonding the two substrates to each other and hardening the sealant, printing a sealant, bonding the substrates each other, and hardening the sealant and an inspection process line of cutting the bonded substrates into panel units and grinding and inspecting the unit panels.

Abstract: A composition of (i) an organometallic precursor containing a hydrazine compound coordinating with a central metal thereof and (ii) an organometallic compound of a main group metal and a method of forming metal film or pattern using this composition.

Abstract: There is provided a semiconductor memory device having a multibank in which a single large memory cell is divided into a plurality of banks without increasing power consumption and chip size. In the semiconductor memory device, a memory cell array is divided into a plurality of banks arranged alternately, and each bank includes a plurality of unit memory cell arrays. In addition, column selection lines of each bank are connected to alternate output ports of a column decoder, and the column decoder enables the column selection lines of a bank selected from the plurality of banks in response to address decoding signals and bank selection signals.

Abstract: A method of controlling an isolation gate of a semiconductor memory device and a circuit therefor are disclosed. The method includes the steps of generating a refresh row active signal, generating a plurality of block select signals, generating a latch isolation control signal and controlling an isolation gate. The refresh row active signal is activated for a constant period. A plurality of block select signals are selectively activated when the refresh row active signal is active. The latch isolation control signal is set according to a block select signal and reset by an adjacent block select signal related to the other isolation gate connected to the same bit line sense amplifier of the block. In the step of controlling the isolation gate, when the latch isolation control signal is active, the isolation gates are turned on, and the other isolation gates connected to the same bit line sense amplifier are turned off.