Patents by Inventor Hae Soon Oh

Hae Soon Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998065
    Abstract: A memory device includes a memory cell block including a plurality of memory cells. The memory device also includes peripheral circuits configured to perform an erase operation by a gate induce drain leakage (GIDL) method by applying a first erase voltage and a second erase voltage to a source line of the memory cell block. The memory device further includes control logic configured to control the peripheral circuits to sequentially perform an operation of applying the first erase voltage and an operation of applying the second erase voltage during the erase operation, wherein memory cells having a plurality of program states, among the plurality of memory cells, are erased to have a pre-erase state during the operation of applying the first erase voltage.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventor: Hae Soon Oh
  • Publication number: 20200321066
    Abstract: A memory device includes a memory cell block including a plurality of memory cells. The memory device also includes peripheral circuits configured to perform an erase operation by a gate induce drain leakage (GIDL) method by applying a first erase voltage and a second erase voltage to a source line of the memory cell block. The memory device further includes control logic configured to control the peripheral circuits to sequentially perform an operation of applying the first erase voltage and an operation of applying the second erase voltage during the erase operation, wherein memory cells having a plurality of program states, among the plurality of memory cells, are erased to have a pre-erase state during the operation of applying the first erase voltage.
    Type: Application
    Filed: October 31, 2019
    Publication date: October 8, 2020
    Applicant: SK hynix Inc.
    Inventor: Hae Soon OH
  • Patent number: 10685712
    Abstract: An operating method of the semiconductor memory device including a plurality of memory cells each having one of “n” number of program statuses as a target program status. The operating method includes performing a program operation to the memory cells according to one of first to third program mode set until a first condition is met; performing the program operation to the memory cells according to another one of first to third program mode set until a second condition is met; and performing the program operation to the memory cells according to a remaining one of first to third program mode set.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: June 16, 2020
    Assignee: SK hynix Inc.
    Inventor: Hae Soon Oh
  • Publication number: 20190035475
    Abstract: An operating method of the semiconductor memory device including a plurality of memory cells each having one of “n” number of program statuses as a target program status. The operating method includes performing a program operation to the memory cells according to one of first to third program mode set until a first condition is met; performing the program operation to the memory cells according to another one of first to third program mode set until a second condition is met; and performing the program operation to the memory cells according to a remaining one of first to third program mode set.
    Type: Application
    Filed: October 4, 2018
    Publication date: January 31, 2019
    Inventor: Hae Soon OH
  • Patent number: 10121545
    Abstract: An operating method of a semiconductor memory device including a plurality of memory cells each having one of “n” number of program statuses as a target program status, the operating method comprising: setting a first group of the memory cells, which have a first group of the program statuses as the target program status, to a program permit mode; setting a second group of the memory cells, which have a second group of the program statuses as the target program status, to a program inhibit mode; performing a program operation and a program verification operation to an i-th one of the “n” program statuses in ascending order of level of the program statuses; and changing one or more of the memory cells of the first group of the memory cells having the i-th program status from the program permit mode to the program inhibit mode, and one or more of the memory cells of the second group of the memory cells having an (i+k)th program status to from the program inhibit mode to the program permit mode, upon success of
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: November 6, 2018
    Assignee: SK Hynix Inc.
    Inventor: Hae Soon Oh
  • Publication number: 20170148520
    Abstract: There are provided an operating method of a semiconductor memory device including a plurality of memory cells each having one of “n” number of program statuses as a target program status, the operating method comprising: setting a first group of the memory cells, which have a first group of the program statuses as the target program status, to a program permit mode; setting a second group of the memory cells, which have a second group of the program statuses as the target program status, to a program inhibit mode; performing a program operation and a program verification operation to an i-th one of the “n” program statuses in ascending order of level of the program statuses; and changing one or more of the memory cells of the first group of the memory cells having the i-th program status from the program permit mode to the program inhibit mode, and one or more of the memory cells of the second group of the memory cells having an (i+k)th program status to from the program inhibit mode to the program permit mod
    Type: Application
    Filed: April 15, 2016
    Publication date: May 25, 2017
    Inventor: Hae Soon OH
  • Patent number: 9627078
    Abstract: A semiconductor device includes a memory array including memory blocks; and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the program loop is performed by controlling a target threshold voltage value of the selection transistors based on a difference between a cell current value of the selected memory block and a reference cell current value.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: April 18, 2017
    Assignee: SK Hynix Inc.
    Inventors: Yoo Nam Jeon, Keon Soo Shim, Hae Soon Oh, Bong Yeol Park
  • Patent number: 9620224
    Abstract: A semiconductor device includes a memory array including memory blocks, and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the operation circuit performs the program loop on the selection transistors so that a difference occurs between threshold voltages of the selection transistors and a target threshold voltage based on a difference between a cell current value of the selected memory block and a reference cell current value.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: April 11, 2017
    Assignee: SK Hynix Inc.
    Inventors: Yoo Nam Jeon, Keon Soo Shim, Hae Soon Oh, Bong Yeol Park
  • Publication number: 20160232975
    Abstract: A semiconductor memory device may include a memory array including memory strings coupled between bit lines and a common source line. The semiconductor memory device may include a peripheral circuit coupled to the memory array through the bit lines. The peripheral circuit may be configured to generate a bit line voltage varied according to a temperature of the memory array and provide the bit line voltage to a selected bit line among the bit lines. The peripheral circuit may provide a program inhibit voltage to a non-selected bit line during a program operation.
    Type: Application
    Filed: July 7, 2015
    Publication date: August 11, 2016
    Inventor: Hae Soon OH
  • Publication number: 20160172047
    Abstract: A semiconductor device includes a memory array including memory blocks; and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the program loop is performed by controlling a target threshold voltage value of the selection transistors based on a difference between a cell current value of the selected memory block and a reference cell current value.
    Type: Application
    Filed: February 9, 2016
    Publication date: June 16, 2016
    Inventors: Yoo Nam JEON, Keon Soo SHIM, Hae Soon OH, Bong Yeol PARK
  • Publication number: 20160125946
    Abstract: A semiconductor device includes a memory array including memory blocks, and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the operation circuit performs the program loop on the selection transistors so that a difference occurs between threshold voltages of the selection transistors and a target threshold voltage based on a difference between a cell current value of the selected memory block and a reference cell current value.
    Type: Application
    Filed: March 17, 2015
    Publication date: May 5, 2016
    Inventors: Yoo Nam JEON, Keon Soo SHIM, Hae Soon OH, Bong Yeol PARK
  • Patent number: 5632392
    Abstract: A foldable container comprises a base (20), a first pair of opposing side walls (3,3') hingedly mounted at one pair of opposing edges of the base, a second pair of opposing side walls (2,2') hingedly mounted at one pair of opposing edges of the base and including flanges (7) extending from both side end regions of the second pair of side walls toward the first pair of opposing side walls, and connecting means for providing toothed engagements between the flanges of the second pair of side walls and the corresponding lateral end regions of the first pair of side walls in the standing-up position. The foldable container can be easily folded when empty and stand up with good stiffness when using.
    Type: Grant
    Filed: November 15, 1995
    Date of Patent: May 27, 1997
    Inventor: Hae Soon Oh