Patents by Inventor Hae Soon Oh
Hae Soon Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11956997Abstract: A display device according to an exemplary embodiment includes: a substrate including a display area and a transmission area; a metal blocking layer disposed in the display area of the substrate; an inorganic insulating layer disposed on the metal blocking film; a transistor disposed on the inorganic insulating layer; an emission layer connected to the transistor; and a light blocking layer and a color filter disposed on the emission layer of the display area, wherein the edge of the light blocking layer is protruded toward the transmission area more than the edge of the metal blocking layer.Type: GrantFiled: August 23, 2021Date of Patent: April 9, 2024Assignee: Samsung Display Co., Ltd.Inventors: Se Wan Son, Nak Cho Choi, Moo Soon Ko, Dong Hyun Son, Sang Hoon Oh, Jin Goo Jung, Kyung Hyun Choi, Hae-Yeon Lee, Seong Min Cho
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Patent number: 10998065Abstract: A memory device includes a memory cell block including a plurality of memory cells. The memory device also includes peripheral circuits configured to perform an erase operation by a gate induce drain leakage (GIDL) method by applying a first erase voltage and a second erase voltage to a source line of the memory cell block. The memory device further includes control logic configured to control the peripheral circuits to sequentially perform an operation of applying the first erase voltage and an operation of applying the second erase voltage during the erase operation, wherein memory cells having a plurality of program states, among the plurality of memory cells, are erased to have a pre-erase state during the operation of applying the first erase voltage.Type: GrantFiled: October 31, 2019Date of Patent: May 4, 2021Assignee: SK hynix Inc.Inventor: Hae Soon Oh
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Publication number: 20200321066Abstract: A memory device includes a memory cell block including a plurality of memory cells. The memory device also includes peripheral circuits configured to perform an erase operation by a gate induce drain leakage (GIDL) method by applying a first erase voltage and a second erase voltage to a source line of the memory cell block. The memory device further includes control logic configured to control the peripheral circuits to sequentially perform an operation of applying the first erase voltage and an operation of applying the second erase voltage during the erase operation, wherein memory cells having a plurality of program states, among the plurality of memory cells, are erased to have a pre-erase state during the operation of applying the first erase voltage.Type: ApplicationFiled: October 31, 2019Publication date: October 8, 2020Applicant: SK hynix Inc.Inventor: Hae Soon OH
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Patent number: 10685712Abstract: An operating method of the semiconductor memory device including a plurality of memory cells each having one of “n” number of program statuses as a target program status. The operating method includes performing a program operation to the memory cells according to one of first to third program mode set until a first condition is met; performing the program operation to the memory cells according to another one of first to third program mode set until a second condition is met; and performing the program operation to the memory cells according to a remaining one of first to third program mode set.Type: GrantFiled: October 4, 2018Date of Patent: June 16, 2020Assignee: SK hynix Inc.Inventor: Hae Soon Oh
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Publication number: 20190035475Abstract: An operating method of the semiconductor memory device including a plurality of memory cells each having one of “n” number of program statuses as a target program status. The operating method includes performing a program operation to the memory cells according to one of first to third program mode set until a first condition is met; performing the program operation to the memory cells according to another one of first to third program mode set until a second condition is met; and performing the program operation to the memory cells according to a remaining one of first to third program mode set.Type: ApplicationFiled: October 4, 2018Publication date: January 31, 2019Inventor: Hae Soon OH
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Patent number: 10121545Abstract: An operating method of a semiconductor memory device including a plurality of memory cells each having one of “n” number of program statuses as a target program status, the operating method comprising: setting a first group of the memory cells, which have a first group of the program statuses as the target program status, to a program permit mode; setting a second group of the memory cells, which have a second group of the program statuses as the target program status, to a program inhibit mode; performing a program operation and a program verification operation to an i-th one of the “n” program statuses in ascending order of level of the program statuses; and changing one or more of the memory cells of the first group of the memory cells having the i-th program status from the program permit mode to the program inhibit mode, and one or more of the memory cells of the second group of the memory cells having an (i+k)th program status to from the program inhibit mode to the program permit mode, upon success ofType: GrantFiled: April 15, 2016Date of Patent: November 6, 2018Assignee: SK Hynix Inc.Inventor: Hae Soon Oh
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Publication number: 20170148520Abstract: There are provided an operating method of a semiconductor memory device including a plurality of memory cells each having one of “n” number of program statuses as a target program status, the operating method comprising: setting a first group of the memory cells, which have a first group of the program statuses as the target program status, to a program permit mode; setting a second group of the memory cells, which have a second group of the program statuses as the target program status, to a program inhibit mode; performing a program operation and a program verification operation to an i-th one of the “n” program statuses in ascending order of level of the program statuses; and changing one or more of the memory cells of the first group of the memory cells having the i-th program status from the program permit mode to the program inhibit mode, and one or more of the memory cells of the second group of the memory cells having an (i+k)th program status to from the program inhibit mode to the program permit modType: ApplicationFiled: April 15, 2016Publication date: May 25, 2017Inventor: Hae Soon OH
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Patent number: 9627078Abstract: A semiconductor device includes a memory array including memory blocks; and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the program loop is performed by controlling a target threshold voltage value of the selection transistors based on a difference between a cell current value of the selected memory block and a reference cell current value.Type: GrantFiled: February 9, 2016Date of Patent: April 18, 2017Assignee: SK Hynix Inc.Inventors: Yoo Nam Jeon, Keon Soo Shim, Hae Soon Oh, Bong Yeol Park
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Patent number: 9620224Abstract: A semiconductor device includes a memory array including memory blocks, and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the operation circuit performs the program loop on the selection transistors so that a difference occurs between threshold voltages of the selection transistors and a target threshold voltage based on a difference between a cell current value of the selected memory block and a reference cell current value.Type: GrantFiled: March 17, 2015Date of Patent: April 11, 2017Assignee: SK Hynix Inc.Inventors: Yoo Nam Jeon, Keon Soo Shim, Hae Soon Oh, Bong Yeol Park
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Publication number: 20160232975Abstract: A semiconductor memory device may include a memory array including memory strings coupled between bit lines and a common source line. The semiconductor memory device may include a peripheral circuit coupled to the memory array through the bit lines. The peripheral circuit may be configured to generate a bit line voltage varied according to a temperature of the memory array and provide the bit line voltage to a selected bit line among the bit lines. The peripheral circuit may provide a program inhibit voltage to a non-selected bit line during a program operation.Type: ApplicationFiled: July 7, 2015Publication date: August 11, 2016Inventor: Hae Soon OH
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Publication number: 20160172047Abstract: A semiconductor device includes a memory array including memory blocks; and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the program loop is performed by controlling a target threshold voltage value of the selection transistors based on a difference between a cell current value of the selected memory block and a reference cell current value.Type: ApplicationFiled: February 9, 2016Publication date: June 16, 2016Inventors: Yoo Nam JEON, Keon Soo SHIM, Hae Soon OH, Bong Yeol PARK
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Publication number: 20160125946Abstract: A semiconductor device includes a memory array including memory blocks, and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the operation circuit performs the program loop on the selection transistors so that a difference occurs between threshold voltages of the selection transistors and a target threshold voltage based on a difference between a cell current value of the selected memory block and a reference cell current value.Type: ApplicationFiled: March 17, 2015Publication date: May 5, 2016Inventors: Yoo Nam JEON, Keon Soo SHIM, Hae Soon OH, Bong Yeol PARK
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Patent number: 5632392Abstract: A foldable container comprises a base (20), a first pair of opposing side walls (3,3') hingedly mounted at one pair of opposing edges of the base, a second pair of opposing side walls (2,2') hingedly mounted at one pair of opposing edges of the base and including flanges (7) extending from both side end regions of the second pair of side walls toward the first pair of opposing side walls, and connecting means for providing toothed engagements between the flanges of the second pair of side walls and the corresponding lateral end regions of the first pair of side walls in the standing-up position. The foldable container can be easily folded when empty and stand up with good stiffness when using.Type: GrantFiled: November 15, 1995Date of Patent: May 27, 1997Inventor: Hae Soon Oh