Patents by Inventor Hae Uk LEE
Hae Uk LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127892Abstract: There are provided a memory device and an operating method of the memory device. The memory device includes: a memory block including a plurality of sub-blocks; a peripheral circuit for performing first program and erase operations in a first manner in a first sub-block, among the plurality of sub-blocks, and performing second program and erase operations in a second manner in a second sub-block, among the plurality of sub-blocks; and a control circuit configured to, when a cycling number of the second program and erase operations that are performed in the second sub-block is equal to or greater than a reference number, control the peripheral circuit to perform a compensation operation that compensates for a threshold voltage of memory cells included in the first sub-block.Type: ApplicationFiled: April 6, 2023Publication date: April 18, 2024Applicant: SK hynix Inc.Inventors: Dong Uk LEE, Yun Cheol KIM, Hae Chang YANG
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Publication number: 20240118813Abstract: A semiconductor memory device and a method of operating the semiconductor memory device are provided. The semiconductor memory device includes a memory block including a plurality of sub-blocks, a peripheral circuit configured to perform a program operation on the memory block, and control logic configured to control the peripheral circuit to perform the program operation on the memory block, wherein the program operation comprises programming to program normal data to a first sub-block, allocated to be a normal sub-block, among the plurality of sub-blocks, and programming parity data of the normal data to a second sub-block, allocated to be a backup block, among the plurality of sub-blocks.Type: ApplicationFiled: March 30, 2023Publication date: April 11, 2024Applicant: SK hynix Inc.Inventors: Dong Uk LEE, Hae Chang YANG, Hun Wook LEE
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Patent number: 11943930Abstract: A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.Type: GrantFiled: June 14, 2023Date of Patent: March 26, 2024Assignee: SK hynix Inc.Inventors: Dong Uk Lee, Hae Chang Yang
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Publication number: 20240074188Abstract: A semiconductor device may include a source line, a bit line, and a gate structure located between the source line and the bit line. The gate structure may include conductive layers and insulating layers that are alternately stacked. The semiconductor device may include a topological insulator that may extend from the bit line to the source line through the gate structure. The topological insulator may include a non-conductor region and semiconductor regions coupled to the non-conductor region and located at a sidewall of the topological insulator. The semiconductor device may also include a memory layer surrounding the topological insulator.Type: ApplicationFiled: February 10, 2023Publication date: February 29, 2024Applicant: SK hynix Inc.Inventors: Dong Uk LEE, Hae Chang YANG
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Publication number: 20240074175Abstract: A CMOS device, and a method of manufacturing the same, includes a semiconductor substrate and a trench formed in the semiconductor substrate. The CMOS device also includes an oxide semiconductor layer disposed in the trench, the oxide semiconductor layer including a source region, a drain region, and a channel region between the source region and the drain region. The CMOS device further includes a buffer layer between the oxide semiconductor layer and the semiconductor substrate, a gate insulating layer on the oxide semiconductor layer, a gate electrode disposed on the gate insulating layer over the channel region of the oxide semiconductor layer, and impurities distributed in each of the source region and the drain region of the oxide semiconductor layer.Type: ApplicationFiled: February 23, 2023Publication date: February 29, 2024Applicant: SK hynix Inc.Inventors: Dong Uk LEE, Hae Chang YANG
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Patent number: 11914885Abstract: The present disclosure provides a memory controller including a state detector detecting whether the memory device is in an idle state, a program controller, based on detection information that indicates a state of the memory device, selecting neighboring strings that are adjacent to a string that is coupled to a memory cell, among the memory cells, on which a program operation or a read operation was performed before the detecting, selecting monitoring memory cells that are coupled to at least one word line, the memory cells being a part of the neighboring strings, and controlling the memory device to perform a plurality of loops to program the monitoring memory cells, and a bad block selector selecting a memory block with the monitoring memory cells as a bad block based on a rate of increase in threshold voltage of a threshold voltage distribution of the monitoring memory cells.Type: GrantFiled: January 17, 2022Date of Patent: February 27, 2024Assignee: SK hynix Inc.Inventors: Dong Uk Lee, Hae Chang Yang, Hun Wook Lee
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Patent number: 9324445Abstract: A high-voltage switching device for a flash memory includes at least one pumping transistor which includes one junction terminal and another junction terminal which are commonly connected to a control signal, and a gate terminal connected to a select signal. The high-voltage switching device also includes at least one switching transistor that includes one junction terminal connected to an input signal, another junction terminal connected to an output signal, and a gate terminal connected to the select signal. A layout of the high-voltage switching device includes a pumping active area in which the one junction terminal and the another junction terminal of the pumping transistor are disposed; a control interconnection area in which an interconnection of the control signal is wired; and a select interconnection area in which an interconnection of the select signal is wired.Type: GrantFiled: May 28, 2015Date of Patent: April 26, 2016Assignees: FIDELIX CO., LTD., NEMOSTECH CO., LTD.Inventors: Hae Uk Lee, Man Seok Soh
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Publication number: 20150364203Abstract: A high-voltage switching device for a flash memory includes at least one pumping transistor which includes one junction terminal and another junction terminal which are commonly connected to a control signal, and a gate terminal connected to a select signal. The high-voltage switching device also includes at least one switching transistor that includes one junction terminal connected to an input signal, another junction terminal connected to an output signal, and a gate terminal connected to the select signal. A layout of the high-voltage switching device includes a pumping active area in which the one junction terminal and the another junction terminal of the pumping transistor are disposed; a control interconnection area in which an interconnection of the control signal is wired; and a select interconnection area in which an interconnection of the select signal is wired.Type: ApplicationFiled: May 28, 2015Publication date: December 17, 2015Inventors: Hae Uk LEE, Man Seok SOH
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Publication number: 20130093472Abstract: A semiconductor integrated circuit includes a driving unit, a first current path and a second current path. The driving unit applies a power supply voltage to a drive node in response to a control signal. The first current path couples the drive node and an output node. The second current path couples the drive node and the output node. The first current path and the second current path are coupled in parallel between the drive node and the output node.Type: ApplicationFiled: December 30, 2011Publication date: April 18, 2013Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hae Uk LEE, Chang Hyuk LEE, Jae Yong CHA, Ha Min SUNG, Yi Seul PARK