Patents by Inventor Hae Wang Lee
Hae Wang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973109Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.Type: GrantFiled: November 15, 2021Date of Patent: April 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Hun Kim, Jae Seok Yang, Hae Wang Lee
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Publication number: 20240063259Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.Type: ApplicationFiled: November 1, 2023Publication date: February 22, 2024Inventors: Young-Hun KIM, Jae Seok YANG, Hae Wang LEE
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Patent number: 11710736Abstract: A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.Type: GrantFiled: December 7, 2020Date of Patent: July 25, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Hae-Wang Lee
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Publication number: 20230215868Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.Type: ApplicationFiled: February 28, 2023Publication date: July 6, 2023Inventors: YOUNG-HUN KIM, JAE-SEOK YANG, HAE-WANG LEE
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Patent number: 11600639Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.Type: GrantFiled: November 2, 2020Date of Patent: March 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Hun Kim, Jae-Seok Yang, Hae-Wang Lee
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Patent number: 11335682Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.Type: GrantFiled: July 3, 2020Date of Patent: May 17, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-hyuck Choi, Hae-wang Lee, Hyoun-jee Ha, Chul-hong Park
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Publication number: 20220077284Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.Type: ApplicationFiled: November 15, 2021Publication date: March 10, 2022Inventors: Young-Hun KIM, Jae Seok YANG, Hae Wang LEE
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Patent number: 11195910Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.Type: GrantFiled: December 10, 2018Date of Patent: December 7, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Hun Kim, Jae Seok Yang, Hae Wang Lee
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Publication number: 20210091074Abstract: A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.Type: ApplicationFiled: December 7, 2020Publication date: March 25, 2021Inventor: HAE-WANG LEE
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Patent number: 10957765Abstract: A semiconductor device is provided including a substrate, a first gate structure, a first contact plug and a power rail. The substrate includes first and second cell regions extending in a first direction, and a power rail region connected to each of opposite ends of the first and second cell regions in a second direction. The first gate structure extends in the second direction from a boundary area between the first and second cell regions to the power rail region. The first contact plug is formed on the power rail region, and contacts an upper surface of the first gate structure. The power rail extends in the first direction on the power rail region, and is electrically connected to the first contact plug. The power rail supplies a turn-off signal to the first gate structure through the first contact plug to electrically insulate the first and second cell regions.Type: GrantFiled: August 1, 2018Date of Patent: March 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Pan-Jae Park, Jae-Seok Yang, Young-Hun Kim, Hae-Wang Lee, Kwan-Young Chun
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Publication number: 20210074729Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.Type: ApplicationFiled: November 2, 2020Publication date: March 11, 2021Inventors: Young-Hun Kim, Jae-Seok Yang, Hae-Wang Lee
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Patent number: 10879237Abstract: A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.Type: GrantFiled: December 21, 2018Date of Patent: December 29, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Hae-Wang Lee
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Patent number: 10872859Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a buried conductive layer disposed adjacent to the active region on the substrate and extending in the first direction, a gate electrode intersecting the active region and extending in a second direction crossing the first direction, a source/drain layer disposed on the active region on one side of the gate electrode, a gate isolation pattern disposed on the buried conductive layer so as to be disposed adjacent to one end of the gate electrode, and extending in the first direction, and a contact plug disposed on the source/drain layer, electrically connected to the buried conductive layer, and in contact with the gate isolation pattern.Type: GrantFiled: April 11, 2019Date of Patent: December 22, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Young Hun Kim, Jae Seok Yang, Hae Wang Lee
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Publication number: 20200335500Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.Type: ApplicationFiled: July 3, 2020Publication date: October 22, 2020Inventors: Jung-hyuck CHOI, Hae-wang LEE, Hyoun-jee HA, Chul-hong PARK
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Patent number: 10777553Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.Type: GrantFiled: March 25, 2019Date of Patent: September 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-hyuck Choi, Hae-wang Lee, Hyoun-jee Ha, Chul-hong Park
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Publication number: 20200098681Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a buried conductive layer disposed adjacent to the active region on the substrate and extending in the first direction, a gate electrode intersecting the active region and extending in a second direction crossing the first direction, a source/drain layer disposed on the active region on one side of the gate electrode, a gate isolation pattern disposed on the buried conductive layer so as to be disposed adjacent to one end of the gate electrode, and extending in the first direction, and a contact plug disposed on the source/drain layer, electrically connected to the buried conductive layer, and in contact with the gate isolation pattern.Type: ApplicationFiled: April 11, 2019Publication date: March 26, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Young Hun Kim, Jae Seok YANG, Hae Wang LEE
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Publication number: 20200043945Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.Type: ApplicationFiled: February 7, 2019Publication date: February 6, 2020Inventors: YOUNG-HUN KIM, JAE-SEOK YANG, HAE-WANG LEE
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Publication number: 20190386099Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.Type: ApplicationFiled: December 10, 2018Publication date: December 19, 2019Inventors: Young-Hun KIM, Jae Seok YANG, Hae Wang LEE
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Publication number: 20190221563Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.Type: ApplicationFiled: March 25, 2019Publication date: July 18, 2019Inventors: Jung-hyuck CHOI, Hae-wang LEE, Hyoun-jee HA, Chul-hong PARK
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Patent number: 10319720Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.Type: GrantFiled: December 20, 2017Date of Patent: June 11, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-hyuck Choi, Hae-wang Lee, Hyoun-jee Ha, Chul-hong Park