Abstract: A capacitor type voltage divider circuit is disclosed. The divider has a plurality of reference voltage signals applied from an external source. A plurality of switching sections are provided for switching the reference voltage signals from the source in response to first and second clock signals. A plurality of dividing sections are provided which are each comprised of two capacitors for dividing the voltage signals from the switching section into a predetermined value. With the dividing circuit, precise levels of reference voltage signals are obtained and power consumption is low without an increase in size or lowering of operational speed.

Abstract: Disclosed is a low power-consumption type comparator circuit having two input terminals for receiving two input signals, one of which is an input reference signal and the other of which is an input comparison signal, and two output terminals, the circuit comprising signal converting portion for converting the input signals into current signals, respectively; switching portion for controlling transmission of the current signals to output terminals of the circuit in response to a latch signal indicating a latch operation or a normal operation of the circuit; high level holding portion for maintaining each voltage level of the output terminals to a logical high-state only when the latch operation of the circuit is not performed; amplifying/determining portion for amplifying the current signals and determining logical level of the input comparison signal; and output feedback portion for receiving output signals of the output terminals and enabling to make a current flowing in the circuit to a zero-state, only whi

Abstract: Disclosed is a data and clock recovery circuit possible to restore data signals and synchronizing clocks which have been distorted during transmission over the communication line, which is comprised of the following: main oscillation loop that maintains operating frequency by using the input data and a self oscillation loop that operates using reference clock embedded within multiplex communication devices when communication lines get shorted or when power is restored after an outage; loop selecting switch which selects the main oscillation loop during normal operating mode and selects the self oscillation loop when communication line shorts or when the power is being restored; data signal monitor which connects to the loop selecting switch and determines communication line shorting by monitoring data transmission; power supply monitor which connects to the loop selecting switch and monitors the restoration of power after an outage.