Abstract: A neural network accelerator includes a control circuit configured to control a learning operation for a neural network by performing a plurality of learning steps; an operation processor configured to perform the learning operation under the control of the control circuit; and an operation memory storing the embedding table that has a plurality of embedding entries and coupled to the operation processor, wherein the operation processor performs a first embedding operation using an embedding entry required for a current learning step, and performs a second embedding operation using an embedding entry that is required for a next learning step and is not affected by the current learning step.