Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on a winding axis to define a core and an outer circumference. The first electrode includes a first active material portion coated with an active material layer and a first uncoated portion not coated with an active material layer along a winding direction. At least a part of the first uncoated portion is defined as an electrode tab by itself. The first uncoated portion includes a first portion adjacent to the core of the electrode assembly, a second portion adjacent to the outer circumference of the electrode assembly, and a third portion interposed between the first portion and the second portion. The first portion or the second portion has a smaller height than the third portion in the winding axis direction.

Abstract: A gas diffuser plate in a cyclic deposition chamber is disclosed. The gas diffuser plate as fabricated comprises a substrate diffuser plate having a substrate emissivity and a coating formed on the substrate diffuser plate. The gas diffuser plate having the substrate diffuser plate coated with the coating has an emissivity higher than the substrate emissivity. The coating comprises a first layer formed on the substrate diffuser plate and comprising a first material configured to modulate the emissivity of the gas diffuser plate, and a second layer comprising a second corrosion-resistant material. The first material comprises titanium nitride oxide (TiNxOy). The emissivity of the gas diffuser plate is at least partially based on the ratio of nitrogen and oxygen in TiNxOy.

Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on an axis to define a core and an outer circumference. The first electrode includes an uncoated portion at a long side end thereof and exposed out of the separator along a winding axis direction of the electrode assembly. A part of the uncoated portion is bent in a radial direction of the electrode assembly to form a bending surface region that includes overlapping layers of the uncoated portion, and in a partial region of the bending surface region, the number of stacked layers of the uncoated portion is 10 or more in the winding axis direction of the electrode assembly.

Abstract: The present invention relates to an image encoding and decoding technique, and more particularly, to an image encoder and decoder using unidirectional prediction. The image encoder includes a dividing unit to divide a macro block into a plurality of sub-blocks, a unidirectional application determining unit to determine whether an identical prediction mode is applied to each of the plurality of sub-blocks, and a prediction mode determining unit to determine a prediction mode with respect to each of the plurality of sub-blocks based on a determined result of the unidirectional application determining unit.

Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.

Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.

Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.

Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.

Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.

Abstract: A display device according to the present disclosure comprises a substrate including a display area and a non-display area, pixel circuits each including at least one n-type transistor and at least one p-type transistor and arranged in the display area, and a gate driving circuit included in the non-display area and outputting a first scan signal for applying a data voltage to driving transistors of the pixel circuits for an initialization time and a second scan signal that represents a same logic voltage as the first scan signal for the initialization time and represents a logic voltage reverse to the first scan signal for a sampling time. A first scan signal generator and a second scan signal generator are integrated using nodes Q/QB of a logic circuit to reduce a bezel size.

Abstract: An electrode for a dye-sensitized solar cell of the present invention includes a substrate; and a nanocomposite layer including a nanocomposite formed on the substrate, wherein the nanocomposite contains: metal, metal oxide or both; and inorganic materials, a conductive polymer or both.

Abstract: Disclosed is an apparatus for spinning a test tray and an in-line test handler including the above apparatus, wherein the apparatus may include a supporting unit for supporting a test tray transported between first and second chamber units facing in the different directions, wherein the first chamber unit is provided at a predetermined interval from the second chamber unit; a base unit to which the supporting unit is spinnably connected; and a spinning unit which spins the test tray so that semiconductor devices received in the test tray are tested at the same arrangement in each of the first chamber unit and the second chamber unit.

Abstract: Disclosed is an apparatus for spinning a test tray and an in-line test handler including the above apparatus, wherein the apparatus may include a supporting unit for supporting a test tray transported between first and second chamber units facing in the different directions, wherein the first chamber unit is provided at a predetermined interval from the second chamber unit; a base unit to which the supporting unit is spinnably connected; and a spinning unit which spins the test tray so that semiconductor devices received in the test tray are tested at the same arrangement in each of the first chamber unit and the second chamber unit.

Abstract: Provided is a nanocomplex comprising a core consisting of a metal; and a periphery being formed on a surface of the core to surround the core and consisting of an inorganic substance and a conductive polymer.

Abstract: Provided is a nanocomplex comprising a core consisting of a metal; and a periphery being formed on a surface of the core to surround the core and consisting of an inorganic substance and a conductive polymer

Abstract: A test handler includes a loading unit including a loading picker and a loading ascending/descending unit, an unloading unit including an unloading picker and an unloading ascending/descending unit, and a chamber system. A passage site connects the loading unit and the chamber system, and also connects the chamber system and the unloading unit. The arrangement of the handler reduces the time for the loading and unloading processes by performing the loading and unloading processes on separate test trays located at separate loading and unloading positions.

Abstract: An apparatus for transferring packaged chips, a test handler, and a method for manufacturing packaged chips are provided. The apparatus for transferring packaged chips may include a main frame having a coupling member coupled to a base plate and a supporting member coupled to the coupling member, a plurality of first pickers coupled to one side of the supporting member so as to be movable in a horizontal direction, a plurality of second pickers coupled to the other side of the supporting member so as to be movable in the horizontal direction, and a control unit to determine distances by which the first pickers and the second pickers move in the horizontal direction.

Abstract: A handler for handling semiconductor chips during a testing process includes a loading position at which packaged chips are loaded into a test tray, and an unloading position at which the packaged chips are unloaded from the test tray. The test tray follows a path through the handler from the loading position to the unloading position, and from the unloading position to the loading position. By separately performing the loading and unloading operations at these different positions within the handler, malfunctions in loading and unloading pickers that load and unload the chips may be reduced. Further, a malfunction in one picker performing one operation may be prevented from influencing operations of the other picker performing another operation. Additionally, collision between the loading picker and the unloading picker may be prevented.

Abstract: A test handler includes a loading unit including a loading picker and a loading ascending/descending unit, an unloading unit including an unloading picker and an unloading ascending/descending unit, and a chamber system. A passage site connects the loading unit and the chamber system, and also connects the chamber system and the unloading unit. The arrangement of the handler reduces the time for the loading and unloading processes by performing the loading and unloading processes on separate test trays located at separate loading and unloading positions.

Abstract: A handler for handling semiconductor chips during a testing process includes a loading position at which packaged chips are loaded into a test tray, and an unloading position at which the packaged chips are unloaded from the test tray. The test tray follows a path through the handler from the loading position to the unloading position, and from the unloading position to the loading position. By separately performing the loading and unloading operations at these different positions within the handler, malfunctions in loading and unloading pickers that load and unload the chips may be reduced. Further, a malfunction in one picker performing one operation may be prevented from influencing operations of the other picker performing another operation. Additionally, collision between the loading picker and the unloading picker may be prevented.