Patents by Inventor Hae Jun Park
Hae Jun Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250148990Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.Type: ApplicationFiled: January 13, 2025Publication date: May 8, 2025Inventors: Se-Hwan Kim, Tae-Keun Lee, Min-Su Kim, Hae-Jun Park, Young-Taek Hong
-
Patent number: 12230213Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.Type: GrantFiled: September 20, 2023Date of Patent: February 18, 2025Assignee: LG Display Co., Ltd.Inventors: Se-Hwan Kim, Tae-Keun Lee, Min-Su Kim, Hae-Jun Park, Young-Taek Hong
-
Publication number: 20240013725Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.Type: ApplicationFiled: September 20, 2023Publication date: January 11, 2024Inventors: Se-Hwan KIM, Tae-Keun LEE, Min-Su KIM, Hae-Jun PARK, Young-Taek HONG
-
Patent number: 11798482Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.Type: GrantFiled: May 16, 2022Date of Patent: October 24, 2023Assignee: LG Display Co., Ltd.Inventors: Se-Hwan Kim, Tae-Keun Lee, Min-Su Kim, Hae-Jun Park, Young-Taek Hong
-
Publication number: 20220270551Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.Type: ApplicationFiled: May 16, 2022Publication date: August 25, 2022Inventors: Se-Hwan KIM, Tae-Keun LEE, Min-Su KIM, Hae-Jun PARK, Young-Taek HONG
-
Patent number: 11367397Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.Type: GrantFiled: December 18, 2020Date of Patent: June 21, 2022Assignee: LG Display Co., Ltd.Inventors: Se-Hwan Kim, Tae-Keun Lee, Min-Su Kim, Hae-Jun Park, Young-Taek Hong
-
Publication number: 20210201799Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.Type: ApplicationFiled: December 18, 2020Publication date: July 1, 2021Inventors: Se-Hwan KIM, Tae-Keun LEE, Min-Su KIM, Hae-Jun PARK, Young-Taek HONG
-
Patent number: 10991302Abstract: A display device according to the present disclosure comprises a substrate including a display area and a non-display area, pixel circuits each including at least one n-type transistor and at least one p-type transistor and arranged in the display area, and a gate driving circuit included in the non-display area and outputting a first scan signal for applying a data voltage to driving transistors of the pixel circuits for an initialization time and a second scan signal that represents a same logic voltage as the first scan signal for the initialization time and represents a logic voltage reverse to the first scan signal for a sampling time. A first scan signal generator and a second scan signal generator are integrated using nodes Q/QB of a logic circuit to reduce a bezel size.Type: GrantFiled: July 1, 2020Date of Patent: April 27, 2021Assignee: LG Display Co., Ltd.Inventors: Hae-Jun Park, Tae-Keun Lee, Min-Su Kim, Se-Hwan Kim, Young-Taek Hong
-
Publication number: 20160086737Abstract: An electrode for a dye-sensitized solar cell of the present invention includes a substrate; and a nanocomposite layer including a nanocomposite formed on the substrate, wherein the nanocomposite contains: metal, metal oxide or both; and inorganic materials, a conductive polymer or both.Type: ApplicationFiled: April 23, 2014Publication date: March 24, 2016Inventors: Hwa Jung KIM, Hae Jun PARK, Ju Woon LEE
-
Patent number: 9285420Abstract: Disclosed is an apparatus for spinning a test tray and an in-line test handler including the above apparatus, wherein the apparatus may include a supporting unit for supporting a test tray transported between first and second chamber units facing in the different directions, wherein the first chamber unit is provided at a predetermined interval from the second chamber unit; a base unit to which the supporting unit is spinnably connected; and a spinning unit which spins the test tray so that semiconductor devices received in the test tray are tested at the same arrangement in each of the first chamber unit and the second chamber unit.Type: GrantFiled: January 22, 2014Date of Patent: March 15, 2016Assignee: MIRAE CORPORATIONInventors: Kyung Tae Kim, Chan Ho Park, Jae Gue Lee, Ung Hyun Yoo, Hae Jun Park, Kook Hyung Lee, Hyun Chae Chung, Jang Yong Park
-
Publication number: 20140203832Abstract: Disclosed is an apparatus for spinning a test tray and an in-line test handler including the above apparatus, wherein the apparatus may include a supporting unit for supporting a test tray transported between first and second chamber units facing in the different directions, wherein the first chamber unit is provided at a predetermined interval from the second chamber unit; a base unit to which the supporting unit is spinnably connected; and a spinning unit which spins the test tray so that semiconductor devices received in the test tray are tested at the same arrangement in each of the first chamber unit and the second chamber unit.Type: ApplicationFiled: January 22, 2014Publication date: July 24, 2014Applicant: MIRAE CORPORATIONInventors: Kyung Tae KIM, Chan Ho PARK, Jae Gue LEE, Ung Hyun YOO, Hae Jun PARK, Kook Hyung LEE, Hyun Chae CHUNG, Jang Yong PARK
-
Patent number: 8613871Abstract: Provided is a nanocomplex comprising a core consisting of a metal; and a periphery being formed on a surface of the core to surround the core and consisting of an inorganic substance and a conductive polymer.Type: GrantFiled: April 9, 2010Date of Patent: December 24, 2013Assignee: Korea Atomic Energy Research InstituteInventors: Hae Jun Park, Hwa-Jung Kim, Sang Hyun Park
-
Publication number: 20110031450Abstract: Provided is a nanocomplex comprising a core consisting of a metal; and a periphery being formed on a surface of the core to surround the core and consisting of an inorganic substance and a conductive polymerType: ApplicationFiled: April 9, 2010Publication date: February 10, 2011Applicant: KOREA ATOMIC ENERGY RESEARCH INSTITUTEInventors: Hae Jun Park, Hwa-Jung Kim, Sang Hyun Park
-
Patent number: 7772834Abstract: A test handler includes a loading unit including a loading picker and a loading ascending/descending unit, an unloading unit including an unloading picker and an unloading ascending/descending unit, and a chamber system. A passage site connects the loading unit and the chamber system, and also connects the chamber system and the unloading unit. The arrangement of the handler reduces the time for the loading and unloading processes by performing the loading and unloading processes on separate test trays located at separate loading and unloading positions.Type: GrantFiled: July 30, 2008Date of Patent: August 10, 2010Assignee: Mirae CorporationInventors: Jung Ug An, Wan Hee Choi, Hae Jun Park, Kyeong Tae Kim
-
Publication number: 20090237089Abstract: An apparatus for transferring packaged chips, a test handler, and a method for manufacturing packaged chips are provided. The apparatus for transferring packaged chips may include a main frame having a coupling member coupled to a base plate and a supporting member coupled to the coupling member, a plurality of first pickers coupled to one side of the supporting member so as to be movable in a horizontal direction, a plurality of second pickers coupled to the other side of the supporting member so as to be movable in the horizontal direction, and a control unit to determine distances by which the first pickers and the second pickers move in the horizontal direction.Type: ApplicationFiled: December 19, 2008Publication date: September 24, 2009Inventors: Jae Kyung CHO, Hae Jun Park
-
Patent number: 7495463Abstract: A handler for handling semiconductor chips during a testing process includes a loading position at which packaged chips are loaded into a test tray, and an unloading position at which the packaged chips are unloaded from the test tray. The test tray follows a path through the handler from the loading position to the unloading position, and from the unloading position to the loading position. By separately performing the loading and unloading operations at these different positions within the handler, malfunctions in loading and unloading pickers that load and unload the chips may be reduced. Further, a malfunction in one picker performing one operation may be prevented from influencing operations of the other picker performing another operation. Additionally, collision between the loading picker and the unloading picker may be prevented.Type: GrantFiled: February 28, 2008Date of Patent: February 24, 2009Assignee: Mirae CorporationInventors: Jung Ug An, Hae Jun Park, Kyung Min Hyun, Wan Hee Choi
-
Publication number: 20090033352Abstract: A test handler includes a loading unit including a loading picker and a loading ascending/descending unit, an unloading unit including an unloading picker and an unloading ascending/descending unit, and a chamber system. A passage site connects the loading unit and the chamber system, and also connects the chamber system and the unloading unit. The arrangement of the handler reduces the time for the loading and unloading processes by performing the loading and unloading processes on separate test trays located at separate loading and unloading positions.Type: ApplicationFiled: July 30, 2008Publication date: February 5, 2009Inventors: Jung Ug AN, Wan Hee CHOI, Hae Jun PARK, Kyeong Tae KIM
-
Publication number: 20080297140Abstract: A handler for handling semiconductor chips during a testing process includes a loading position at which packaged chips are loaded into a test tray, and an unloading position at which the packaged chips are unloaded from the test tray. The test tray follows a path through the handler from the loading position to the unloading position, and from the unloading position to the loading position. By separately performing the loading and unloading operations at these different positions within the handler, malfunctions in loading and unloading pickers that load and unload the chips may be reduced. Further, a malfunction in one picker performing one operation may be prevented from influencing operations of the other picker performing another operation. Additionally, collision between the loading picker and the unloading picker may be prevented.Type: ApplicationFiled: February 28, 2008Publication date: December 4, 2008Inventors: Jung Ug AN, Hae Jun Park, Kyung Min Hyun, Wan Hee Choi
-
Publication number: 20080012113Abstract: A carrier module for a test tray includes a main body having an insertion slot that passes through the main body. An upright-positionable packaged chip can be inserted into the insertion slot, and a holding unit, provided on the main body holds and releases the upright-positionable packaged chip. The upright positionable packaged chip is held in a position where electrical contacts on the chip package are exposed from the main body so that the chip package can be tested.Type: ApplicationFiled: July 13, 2007Publication date: January 17, 2008Inventor: Hae Jun Park
-
Publication number: 20040116296Abstract: The invention relates to a method for producing sustained-releasing agricultural chemicals. The effective ingredients of the agricultural chemicals are absorbed into a carrier and are released sustainedly. The effect of a injection last about 30 to 40 days, and the concentration of the agricultural chemicals is enough to have an effect. The agricultural chemicals of this invention may save the farmers' labor, reduce costs caused by continuous injections, and decline environmental contamination as an environmentalfriendly agricultural chemicals.Type: ApplicationFiled: April 18, 2003Publication date: June 17, 2004Inventors: Hae-Jun Park, In-Kuk Lee, Hyun-Suk Shin, Mi-Young Rho, Nam-Kyu Kim