Abstract: A laser detecting circuit is provided. The laser detecting circuit includes a latch circuit with a first inverter configured to invert a first output signal at a first node to generate a second output signal at a second node, and a second inverter configured to generate the first output signal based on the second output signal. The second inverter includes a plurality of PMOS transistors connected in series between a first source voltage and the first node, and a plurality of NMOS transistors. A gate of each of the plurality of PMOS transistors is connected to the second node, and a drain of each of the plurality of NMOS transistors is connected to the first node. The plurality of NMOS transistors includes dummy NMOS transistors and normal NMOS transistors.

Abstract: A semiconductor device including a bandgap reference generator that generates a reference voltage; a switch control voltage generator that generates a first reference current based on the reference voltage, and generates an adaptive switch level voltage by distributing the first reference current to a first path and a second path, the first path including a first resistor, and the second path including a second resistor and a first bipolar junction transistor connected in series; and a switch controller that generates a switch control signal for controlling switches included in the bandgap reference generator based on the adaptive switch level voltage. The adaptive switch level voltage has a slope with respect to temperature that is greater than a base-emitter voltage of the first bipolar junction transistor.

Abstract: A clock monitoring circuit includes a clock enable signal generator configured to generate an ultra-high frequency clock enable signal based on a clock enable control signal and a reference clock signal, and an ultra-high frequency detector configured to generate an ultra-high frequency determination signal indicating whether a selection clock signal is an ultra-high frequency signal, based on the selection clock signal, the ultra-high frequency clock enable signal, and the reference clock signal.

Abstract: A temperature sensor includes a first selection circuit outputting one among temperature signals in response to a selection code. A reference voltage generator generates a reference voltage. A control circuit generates a control signal. A second selection circuit outputs the reference voltage and the temperature signal in response to the control signal indicating a voltage conversion condition is satisfied and outputs only the temperature signal in response to the control signal indicating the voltage conversion condition is not satisfied. A converter converts the reference voltage to a voltage digital code and the temperature signal to a temperature digital code in response to the control signal indicating the voltage conversion condition is satisfied and converts only the temperature signal to the temperature digital code in response to the control signal indicating the voltage conversion condition is not satisfied.

Abstract: An electronic device includes circuitry configured to output a first output signal shifting to a logic high level at a first time in response to a supply voltage reaching a first voltage level, output a second output signal shifting to a logic high level at a second time occurring after the first time in response to the supply voltage reaches a second level higher than the first level; and the circuitry includes an AND gate circuit configured to output a reset signal based on the first output signal and the second output signal.

Abstract: A laser detecting circuit is provided. The laser detecting circuit includes a latch circuit with a first inverter configured to invert a first output signal at a first node to generate a second output signal at a second node, and a second inverter configured to generate the first output signal based on the second output signal. The second inverter includes a plurality of PMOS transistors connected in series between a first source voltage and the first node, and a plurality of NMOS transistors. A gate of each of the plurality of PMOS transistors is connected to the second node, and a drain of each of the plurality of NMOS transistors is connected to the first node. The plurality of NMOS transistors includes dummy NMOS transistors and normal NMOS transistors.

Abstract: An electronic device includes circuitry configured to output a first output signal shifting to a logic high level at a first time in response to a supply voltage reaching a first voltage level, output a second output signal shifting to a logic high level at a second time occurring after the first time in response to the supply voltage reaches a second level higher than the first level; and the circuitry includes an AND gate circuit configured to output a reset signal based on the first output signal and the second output signal.

Abstract: A voltage monitoring circuit includes an initializing circuit that outputs an initialization signal generated by delaying a power supply voltage as much as a first delay time, a switching circuit that outputs a switching signal in response to a reset signal, a voltage detecting circuit that outputs a detection signal based on the power supply voltage and stops an operation in response to the switching signal, and an output circuit that outputs the reset signal based on the initialization signal and the detection signal.

Abstract: An electronic device includes circuitry configured to output a first output signal shifting to a logic high level at a first time in response to a supply voltage reaching a first voltage level, output a second output signal shifting to a logic high level at a second time occurring after the first time in response to the supply voltage reaches a second level higher than the first level; and the circuitry includes an AND gate circuit configured to output a reset signal based on the first output signal and the second output signal.

Abstract: An electronic device includes circuitry configured to output a first output signal shifting to a logic high level at a first time in response to a supply voltage reaching a first voltage level, output a second output signal shifting to a logic high level at a second time occurring after the first time in response to the supply voltage reaches a second level higher than the first level; and the circuitry includes an AND gate circuit configured to output a reset signal based on the first output signal and the second output signal.

Abstract: A voltage monitoring circuit includes an initializing circuit that outputs an initialization signal generated by delaying a power supply voltage as much as a first delay time, a switching circuit that outputs a switching signal in response to a reset signal, a voltage detecting circuit that outputs a detection signal based on the power supply voltage and stops an operation in response to the switching signal, and an output circuit that outputs the reset signal based on the initialization signal and the detection signal.