Abstract: A method of forming a relatively fine contact hole using two masks. The two masks may have only their edge portions open, which may overlap each other.

Abstract: A semiconductor device and a method of fabricating same are provided. According to an embodiment, a gate insulating layer and a gate are sequentially formed on a substrate, and a pocket ion implant region is formed at sides and below a portion of the gate at a predetermined depth in the substrate. An LDD ion implant region can be formed between the pocket ion implant region and the surface of the substrate. A spacer is formed on sides of the gate, and a deep source/drain region is formed by ion-implanting BF2 within the substrate at sides of the spacer.

Abstract: A semiconductor device and a method for fabricating the same that includes a drain contact that can prevent bridging between contact metals in metal contact line (M1C) processes. The method includes forming a contact hole extending through an interlayer dielectric film in a space between respective gate electrodes to expose an undercut region, filling the contact hole and the undercut region with a photosensitive material, removing the photosensitive material from the contact hole and then forming a drain contact in the contact hole.

Abstract: A semiconductor device and a fabricating method thereof are provided.

Abstract: A semiconductor device and a method for fabricating the same that includes a drain contact that can prevent bridging between contact metals in metal contact line (M1C) processes. The method includes forming a contact hole extending through an interlayer dielectric film in a space between respective gate electrodes to expose an undercut region, filling the contact hole and the undercut region with a photosensitive material, removing the photosensitive material from the contact hole and then forming a drain contact in the contact hole.

Abstract: In one example embodiment, a method of fabricating a semiconductor device includes various steps. First, an isolation film is formed on a semiconductor substrate to define a field region and an active region. Then, a stack gate structure is formed. Next, a first photoresist and a second photoresist are sequentially formed on the stack gate structure. Then, a patterning process is performed to remove the second photoresist in a source line region. Next, a patterning process is performed to remove the first photoresist in the source line region, to thereby expose the isolation film. Then, the exposed isolation film is removed to expose the semiconductor substrate in the source line region. Finally, a cell source ion implantation process is performed using the patterned second photoresist as an ion injection mask to form a source line having impurity ions implanted thereto in the semiconductor substrate of the source line region.

Abstract: Disclosed is a method of manufacturing an alignment key of a semiconductor device. According to an embodiment, the method includes forming an insulating layer on a semiconductor substrate on which a cell region and a scribe line are defined, forming a photoresist pattern on the insulating layer and etching the insulating layer using the photoresist pattern as an etch mask so as to form a contact hole on the cell region and a mark hole on the scribe line, depositing a metal layer in the contact hole and the mark hole, and planarizing the metal layer so as to form a contact and an alignment mark. The mark hole can be the same size as the contact hole. In addition, the mark hole can be formed in plurality on the scribe line.

Abstract: A method for forming a semiconductor device comprising forming an inter-layer dielectric (ILD) layer on a semiconductor substrate; forming a first trench and second trench in a cell area on the ILD layer, wherein the second trench has a width which is wider than the first trench; forming a first metal layer on the substrate, such that the first metal layer fills the first trench and does not entirely fill the second trench; performing a planarization process on the first metal layer such that the surface of the first metal layer in the first trench and the surface of the substrate has a height which is different than the height of the surface of the first metal layer in the second trench; and forming a plurality of align key and overlay key areas by forming a second metal layer on the surface of the substrate and first metal layer.

Abstract: A dual gate Complementary Metal Oxide Semiconductor (CMOS) device includes a gate electrode of PMOS transistor implanted with germanium and indium ions and formed on a gate insulating film; a gate electrode of NMOS transistor not implanted with germanium and indium ions and formed on the gate insulating film; a source/drain region formed in a substrate exposed at both sides of the gate electrodes of the PMOS and NMOS transistors; and metal silicides formed on the source/drain region and the gate electrodes. A method for manufacturing a dual gate CMOS device, the method includes forming a gate insulating film; forming a polycrystalline silicon layer; forming an ion implantation mask; implanting germanium (Ge) and indium (In) ions into a PMOS transistor region of the substrate; and removing the ion implantation mask, patterning the polycrystalline silicon layer, and forming gate electrodes for PMOS and NMOS transistors.

Abstract: A method of forming a relatively fine contact hole using two masks. The two masks may have only their edge portions open, which may overlap each other.