Abstract: A semiconductor device may include: a mode input control signal generation circuit configured to generate a control pulse when a mode control operation is performed, generate a mode input control signal by delaying the control pulse by a mode delay period, and control the mode delay period on the basis of a restart signal; a read strobe signal generation circuit configured to generate a read strobe signal on the basis of the control pulse; a read delay circuit configured to generate the read input control signal by delaying the read strobe signal by a read delay period; and a read pipe circuit configured to receive mode data on the basis of the mode input control signal, and receive cell data on the basis of the read input control signal.

Abstract: An electronic device may include: a clock divider circuit configured to generate a first internal clock including pulses which are generated in synchronization with odd pulses of a clock, and generate a second internal clock including pulses which are generated in synchronization with even pulses of the clock; and a command decoder configured to generate an odd precharge command and an even precharge command based on a counting signal which is toggled by a chip selection signal and a command/address signal for performing a precharge operation in synchronization with the first internal clock or toggled by the chip selection signal and the command/address signal for performing the precharge operation in synchronization with the second internal clock.

Abstract: A semiconductor device may include: a mode input control signal generation circuit configured to generate a control pulse when a mode control operation is performed, generate a mode input control signal by delaying the control pulse by a mode delay period, and control the mode delay period on the basis of a restart signal; a read strobe signal generation circuit configured to generate a read strobe signal on the basis of the control pulse; a read delay circuit configured to generate the read input control signal by delaying the read strobe signal by a read delay period; and a read pipe circuit configured to receive mode data on the basis of the mode input control signal, and receive cell data on the basis of the read input control signal.

Abstract: An electronic device may include: a clock divider circuit configured to generate a first internal clock including pulses which are generated in synchronization with odd pulses of a clock, and generate a second internal clock including pulses which are generated in synchronization with even pulses of the clock; and a command decoder configured to generate an odd precharge command and an even precharge command based on a counting signal which is toggled by a chip selection signal and a command/address signal for performing a precharge operation in synchronization with the first internal clock or toggled by the chip selection signal and the command/address signal for performing the precharge operation in synchronization with the second internal clock.

Abstract: A test control circuit includes a test mode generation circuit. The test mode generation circuit may be configured to generate, while in a fast access mode, a fast test mode signal based on information included in one of a plurality of mode signals and a fast set signal. The test mode generation circuit may be configured to generate, while in a normal mode, a normal test mode signal based on information included in two or more mode signals from the plurality of mode signals and a normal set signal.

Abstract: A test mode control circuit relating to a technology for controlling a vendor specific test mode is disclosed. The test mode control circuit includes a signal generation circuit configured to generate a plurality of set signals and a plurality of reset signals in response to a plurality of code signals and a predetermined mode register signal; and a plurality of serially-connected latch circuits configured to selectively operate in response to the plurality of set signals and the plurality of reset signals so as to control an entry signal of an output terminal.

Abstract: A test control circuit includes a test mode generation circuit. The test mode generation circuit may be configured to generate, while in a fast access mode, a fast test mode signal based on information included in one of a plurality of mode signals and a fast set signal. The test mode generation circuit may be configured to generate, while in a normal mode, a normal test mode signal based on information included in two or more mode signals from the plurality of mode signals and a normal set signal.

Abstract: A test control circuit includes a test mode generation circuit. The test mode generation circuit may be configured to generate, while in a fast access mode, a fast test mode signal based on information included in one of a plurality of mode signals and a fast set signal. The test mode generation circuit may be configured to generate, while in a normal mode, a normal test mode signal based on information included in two or more mode signals from the plurality of mode signals and a normal set signal.

Abstract: A test control circuit includes a test mode generation circuit. The test mode generation circuit may be configured to generate, while in a fast access mode, a fast test mode signal based on information included in one of a plurality of mode signals and a fast set signal. The test mode generation circuit may be configured to generate, while in a normal mode, a normal test mode signal based on information included in two or more mode signals from the plurality of mode signals and a normal set signal.

Abstract: Provided is a reception circuit provided in a chip, the reception circuit including a controller that generates a reception control signal which is activated for a preset time on a basis of a first control signal individually provided to a plurality of chips, a buffer that receives a second control signal commonly provided to the plurality of chips, and a delay circuit that receives the second control signal from the buffer in response to the reception control signal and provides the second control signal to other elements in the chip.

Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs pre-order address signals, post-order address signals, and an update signal including pulses periodically generated. The semiconductor device generates internal address signals counted by a predetermined number of times according to a combination of the pre-order address signals and a combination of the post-order address signals in response to a pulse of the update signal. The semiconductor device also performs a refresh operation according to a combination of the internal address signals.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output command signals and setting signals. The second semiconductor device may be configured to decode the command signals, extract setting codes from the setting signals, and test a memory cell array accessed by address patterns during at least one operation section corresponding to the setting codes to confirm whether the memory cell array includes at least one failed memory cell.

Abstract: A test mode control circuit relating to a technology for controlling a vendor specific test mode is disclosed. The test mode control circuit includes a signal generation circuit configured to generate a plurality of set signals and a plurality of reset signals in response to a plurality of code signals and a predetermined mode register signal; and a plurality of serially-connected latch circuits configured to selectively operate in response to the plurality of set signals and the plurality of reset signals so as to control an entry signal of an output terminal.

Abstract: A test mode control circuit relating to a technology for controlling a vendor specific test mode is disclosed. The test mode control circuit includes a signal generation circuit configured to generate a plurality of set signals and a plurality of reset signals in response to a plurality of code signals and a predetermined mode register signal; and a plurality of serially-connected latch circuits configured to selectively operate in response to the plurality of set signals and the plurality of reset signals so as to control an entry signal of an output terminal.

Abstract: A semiconductor device may include a boot-up operation circuit configured for executing a boot-up operation during a boot-up operation period after a power supply voltage signal reaches a predetermined level. The boot-up operation circuit may be configured for generating a boot-up period signal. The boot-up period signal may be enabled during the boot-up operation period. The semiconductor device may include a sensing circuit configured for sensing the boot-up period signal and a clock enablement signal to generate a first detection signal and a second detection signal. The semiconductor device may include an initialization circuit configured for executing an initialization operation in response to the first and second detection signals. Related semiconductor systems may also be provided.

Abstract: Provided is a reception circuit provided in a chip, the reception circuit including a controller that generates a reception control signal which is activated for a preset time on a basis of a first control signal individually provided to a plurality of chips, a buffer that receives a second control signal commonly provided to the plurality of chips, and a delay circuit that receives the second control signal from the buffer in response to the reception control signal and provides the second control signal to other elements in the chip.

Abstract: Provided is a reception circuit provided in a chip, the reception circuit including a controller that generates a reception control signal which is activated for a preset time on a basis of a first control signal individually provided to a plurality of chips, a buffer that receives a second control signal commonly provided to the plurality of chips, and a delay circuit that receives the second control signal from the buffer in response to the reception control signal and provides the second control signal to other elements in the chip.

Abstract: A test mode control circuit relating to a technology for controlling a vendor specific test mode is disclosed. The test mode control circuit includes a signal generation circuit configured to generate a plurality of set signals and a plurality of reset signals in response to a plurality of code signals and a predetermined mode register signal; and a plurality of serially-connected latch circuits configured to selectively operate in response to the plurality of set signals and the plurality of reset signals so as to control an entry signal of an output terminal.

Abstract: Provided is a reception circuit provided in a chip, the reception circuit including a controller that generates a reception control signal which is activated for a preset time on a basis of a first control signal individually provided to a plurality of chips, a buffer that receives a second control signal commonly provided to the plurality of chips, and a delay circuit that receives the second control signal from the buffer in response to the reception control signal and provides the second control signal to other elements in the chip.

Abstract: A semiconductor device may include a boot-up operation circuit configured for executing a boot-up operation during a boot-up operation period after a power supply voltage signal reaches a predetermined level. The boot-up operation circuit may be configured for generating a boot-up period signal. The boot-up period signal may be enabled during the boot-up operation period. The semiconductor device may include a sensing circuit configured for sensing the boot-up period signal and a clock enablement signal to generate a first detection signal and a second detection signal. The semiconductor device may include an initialization circuit configured for executing an initialization operation in response to the first and second detection signals. Related semiconductor systems may also be provided.