Abstract: The present invention relates to a small interference RNA (siRNA) for specifically inhibiting the expression of ribosomal protein in cells, and more particularly, to an siRNA that specifically inhibits the expression of endogenous rpS3 protein in cells without influencing tagged overexpressed protein. The siRNAs of the present invention are excellent in terms of economy and efficiency compared to conventional commercially available products.

Abstract: The present invention relates to a small interference RNA (siRNA) for specifically inhibiting the expression of ribosomal protein in cells, and more particularly, to an siRNA that specifically inhibits the expression of endogenous rpS3 protein in cells without influencing tagged overexpressed protein. The siRNAs of the present invention are excellent in terms of economy and efficiency compared to conventional commercially available products.

Abstract: Embodiments relate to an image sensor that may include transistors, a first dielectric, a crystalline semiconductor layer on and/or over the first dielectric, a photodiode, a dummy region, via contacts, and a second dielectric. A photodiode may be formed by implanting impurity ions into a crystalline semiconductor layer to correspond the pixel region. A dummy region may be formed in the crystalline semiconductor layer excepting a region for the photodiode. Via contacts may penetrate the dummy region, and may be connected to the first metal interconnections. A second dielectric may include a plurality of second metal interconnections on and/or over the crystalline semiconductor layer. The plurality of second metal interconnections may electrically connect the via contacts to the photodiode.

Abstract: Provided are an ion implanter for compensating for a wafer cut angle and an ion implantation method using the same. The ion implanter may include an orienter for rotating a wafer mounted on an alignment stage thereof to align a notch of the wafer and a wafer stage for mounting thereon the wafer whose notch has been aligned. The ion implanter may further include an ion implantation angle adjustment unit for adjusting an angle of the wafer stage, a cut angle measurement unit for measuring the wafer cut angle while the wafer is mounted and rotated on the alignment stage, and a controller for controlling the ion implantation angle adjustment unit to compensate for the measured wafer cut angle.

Abstract: Embodiments relate to an image sensor that may include transistors, a first dielectric, a crystalline semiconductor layer on and/or over the first dielectric, a photodiode, a dummy region, via contacts, and a second dielectric. A photodiode may be formed by implanting impurity ions into a crystalline semiconductor layer to correspond the pixel region. A dummy region may be formed in the crystalline semiconductor layer excepting a region for the photodiode. Via contacts may penetrate the dummy region, and may be connected to the first metal interconnections. A second dielectric may include a plurality of second metal interconnections on and/or over the crystalline semiconductor layer. The plurality of second metal interconnections may electrically connect the via contacts to the photodiode.

Abstract: Provided are an ion implanter for compensating for a wafer cut angle and an ion implantation method using the same. The ion implanter may include an orienter for rotating a wafer mounted on an alignment stage thereof to align a notch of the wafer and a wafer stage for mounting thereon the wafer whose notch has been aligned. The ion implanter may further include an ion implantation angle adjustment unit for adjusting an angle of the wafer stage, a cut angle measurement unit for measuring the wafer cut angle while the wafer is mounted and rotated on the alignment stage, and a controller for controlling the ion implantation angle adjustment unit to compensate for the measured wafer cut angle.

Abstract: A transistor and a method for fabricating the same is disclosed, to uniformly provide impurity ions in impurity areas, and to prevent a short channel effect, in which the method for fabricating the transistor includes steps of forming a plurality of channel ion implantation areas having different depths in a first conductive type semiconductor substrate; forming a pillar by selectively etching the first conductive type semiconductor substrate; sequentially depositing a gate insulating layer and a conductive layer for a gate electrode on the first conductive type semiconductor substrate including the pillar; forming the gate electrode by selectively patterning the conductive layer; and forming second conductive type source/drain impurity ion areas in the first conductive type semiconductor substrate corresponding to the top of the pillar and both sidewalls of the pillar.

Abstract: Methods for stabilizing a threshold voltage in an NMOS transistor are disclosed. A disclosed method comprises: forming a gate electrode on an active region in a substrate of a first conductive type; implanting ions of a second conductive type into the active region to form LDD regions; forming spacers on the sidewalls of the gate electrode; implanting ions of the second conductive type into the active region to form second source/drain regions; implanting halo ions into the active region; activating ions in the source/drain regions by conducting a first thermal process; and moving the halo ions toward the surface of the channel under the gate electrode by conducting a second thermal process.

Abstract: A example disclosed semiconductor fabrication method includes forming a well region in a semconductor substrate where device isolation structures are formed, depositing a buffer oxide layer and a nitride layer on the semiconductor substrate, forming a dummy gate by patterning the nitride layer; depositing a liner oxide layer and an insulation layer on the buffer oxide layer and the dummy gate and performing a planarization process, removing the dummy gate and implanting ions, removing the liner oxide layer and the insulation layer and performing a thermal treatment, and forming a polysilicon gate electrode by using the buffer oxide layer as a gate oxide layer.

Abstract: Methods of fabricating a semiconductor devices are disclosed. One example method includes forming a gate insulating layer and a gate electrode on a semiconductor substrate; forming first halo implant regions under the gate electrode in the semiconductor substrate by implanting first conduction type impurities; forming low concentration impurity regions for LDD regions under sides of the gate electrode in the semiconductor substrate by implanting second conduction type impurities at a low concentration; forming second halo implant regions under sides of the gate electrode in the semiconductor substrate by implanting first conduction type impurities; forming high concentration impurity regions for source/drain regions in the semiconductor substrate by implanting second conduction type impurities; and forming junction compensation ion regions between the high concentration impurity regions and the second halo implant regions by implanting first conduction type impurities.

Abstract: A method for fabricating a vertical transistor including forming a first junction area in a semiconductor substrate, forming a polysilicon layer by using an epitaxial growth in the substrate, forming a second junction area in the polysilicon layer, and forming a plug junction area in the polysilicon layer, the plug junction area electrically connected with the first junction area. The method also includes forming a trench by selectively etching and removing the polysilicon layer to expose the first junction area, sequentially depositing a gate insulating layer and a conductive layer for a first gate electrode on the trench and the polysilicon layer, and forming the first gate electrode by selectively patterning the conductive layer.

Abstract: A method of manufacturing a semiconductor device is disclosed. An oxide layer for regulating ion-implantation is formed before the implantation of the impurities into a predetermined region of a P-lightly doped drained (LDD) to regulate the implantation state of P type impurities into the corresponding predetermined region of P-LDD based on the oxide layer for regulating the ion-implantation so that the PMOS side predetermined channel length is elongated longer that the NMOS side predetermined channel length. A method of manufacturing a semiconductor device is also disclosed, wherein separate spacers are selected and formed on a different scales before the implantation of the impurities into predetermined regions of P-LDD and an N-LDD to regulate the implantation state of impurities into the respective predetermined regions of the LDD based on the differently scaled spacers so that the PMOS and NMOS side predetermined channel lengths are selectively regulated.

Abstract: The present invention provides a manufacturing method of a semiconductor device, in which an oxide layer for regulating the ion-implantation is previously formed before the implantation of the impurities into a predetermined region of a P-lightly doped drain (LDD) to optionally regulate the implantation state of P type impurities into the corresponding predetermined region of P-LDD based on the oxide layer for regulating the ion-implantation so that the PMOS side predetermined channel length is elongated longer than the NMOS side predetermined channel length, thus maintaining the finished PMOS and NMOS side channel lengths equal irrespective of diffusion velocity of the impurities even if a substantial annealing process is performed and P type impurities are diffused faster than N type impurities due to their structural difference.