Abstract: A circuit for a phase-locked loop is described herein. The circuit includes a phase frequency detector configured to determine a phase error, a loop filter coupled to the phase frequency detector and configured to provide a clock control signal based on the phase error, and a controller coupled to the phase frequency detector and to the loop filter. The controller is configured to receive the phase error, detect a behavior of the phase error, and, responsive to the behavior of the phase error, perform a response that includes causing the phase frequency detector to adjust the phase error and causing the loop filter to adjust the clock control signal. Thus, the circuit may reduce settling time, overshoot, and/or undershoot in an output clock generated based on the clock control signal.

Abstract: In examples, an electronic device comprises an oscillator circuit configured to provide an output signal and a controller coupled to the oscillator circuit. The controller is configured to receive first and second target rates; dynamically adjust a frequency accuracy of the output signal based on the first target rate; and dynamically adjust an amplitude of the output signal based on the second target rate.

Abstract: A sensor array includes a base for providing a probe signal and a plurality of modular recording sites. Each modular recording site of the plurality of modular recording sites is configured for receiving a signal, for converting the signal into a digital sensor signal and to provide the digital sensor signal to the base. The base is configured for receiving a plurality of digital sensor signals from the plurality of modular recording sites and to process the plurality of digital sensor signals so as to provide the probe signal.

Abstract: In examples, an electronic device comprises an oscillator circuit configured to provide an output signal and a controller coupled to the oscillator circuit. The controller is configured to receive first and second target rates; dynamically adjust a frequency accuracy of the output signal based on the first target rate; and dynamically adjust an amplitude of the output signal based on the second target rate.

Abstract: A sensor array includes a base for providing a probe signal and a plurality of modular recording sites. Each modular recording site of the plurality of modular recording sites is configured for receiving a signal, for converting the signal into a digital sensor signal and to provide the digital sensor signal to the base. The base is configured for receiving a plurality of digital sensor signals from the plurality of modular recording sites and to process the plurality of digital sensor signals so as to provide the probe signal.