Patents by Inventor Haggai Eran
Haggai Eran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240396830Abstract: A device, communication system, and method are provided. In one example, a system for routing traffic is described that includes a network device. The network device includes a plurality of ports to facilitate communication over a plurality of planes in a multiplane network. The network device also includes a first interface that presents the plurality of ports as a single plane agnostic port to software, and a second interface that presents each port in the plurality of ports as a separate port to the software.Type: ApplicationFiled: April 17, 2024Publication date: November 28, 2024Inventors: Haggai Eran, Inbal Gal, Guy Rozenberg Kunievsky, Jason Gunthorpe, Liran Liss, Vladimir Koushnir
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Publication number: 20240338327Abstract: A system comprises a first processing block configured to receive, from a first local resource, a formatted transaction in a format that is not recognizable by a remote endpoint; determine a first transaction category, from among a plurality of transaction categories, of the formatted transaction based on content of the formatted transaction; perform one or operations on the formatted transaction based on the first transaction category to form a reformatted transaction in a format that is recognizable by the remote endpoint; and place the reformatted transaction in a queue for transmission to the remote endpoint.Type: ApplicationFiled: June 18, 2024Publication date: October 10, 2024Inventors: Dimitrios Syrivelis, Paraskevas Bakopoulos, Ioannis (Giannis) Patronas, Elad Mentovich, James Stephen Fields, Haggai Eran, Liran Liss
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Publication number: 20240340242Abstract: A network device for load balancing in a multiplane network comprises a software stack that formats a data flow for transmission, and one or more circuits that identify the formatted data flow as a fixed data flow, and apply software-based load balancing to select a first plane, from among a plurality of planes of the multiplane network, for transmitting one or more data packets of the fixed data flow.Type: ApplicationFiled: April 10, 2023Publication date: October 10, 2024Inventors: Haggai Eran, Omer Shabtai, Gil Bloch, Michael Avimelech Gandelman Milgrom, Guy Rozenberg Kunievsky
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Patent number: 12045178Abstract: A system comprises a first processing block configured to receive, from a first local resource, a formatted transaction in a format that is not recognizable by a remote endpoint; determine a first transaction category, from among a plurality of transaction categories, of the formatted transaction based on content of the formatted transaction; perform one or operations on the formatted transaction based on the first transaction category to form a reformatted transaction in a format that is recognizable by the remote endpoint; and place the reformatted transaction in a queue for transmission to the remote endpoint.Type: GrantFiled: February 16, 2022Date of Patent: July 23, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dimitrios Syrivelis, Paraskevas Bakopoulos, Ioannis (Giannis) Patronas, Elad Mentovich, James Stephen Fields, Jr., Haggai Eran, Liran Liss
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Patent number: 11991073Abstract: A device, communication system, and method are provided. In one example, a system for routing traffic is described that includes a network device. The network device includes a plurality of ports to facilitate communication over a plurality of planes in a multiplane network. The network device also includes a first interface that presents the plurality of ports as a single plane agnostic port to software, and a second interface that presents each port in the plurality of ports as a separate port to the software.Type: GrantFiled: May 22, 2023Date of Patent: May 21, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Haggai Eran, Inbal Gal, Guy Rozenberg Kunievsky, Jason Gunthorpe, Liran Liss, Vladimir Koushnir
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Patent number: 11757796Abstract: In one embodiment, a system includes a peripheral device including a memory access interface to receive from a host device headers of packets, while corresponding payloads of the packets are stored in a host memory of the host device, and descriptors being indicative of respective locations in the host memory at which the corresponding payloads are stored, a data processing unit memory to store the received headers and the descriptors without the payloads of the packets, and a data processing unit to process the received headers, wherein the peripheral device is configured, upon completion of the processing of the received headers by the data processing unit, to fetch the payloads of the packets over the memory access interface from the respective locations in the host memory responsively to respective ones of the descriptors, and packet processing circuitry to receive the headers and payloads of the packets, and process the packets.Type: GrantFiled: September 29, 2021Date of Patent: September 12, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Haggai Eran, Liran Liss, Yuval Shpigelman, Idan Burstein
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Publication number: 20230251980Abstract: A system comprises a first processing block configured to receive, from a first local resource, a formatted transaction in a format that is not recognizable by a remote endpoint; determine a first transaction category, from among a plurality of transaction categories, of the formatted transaction based on content of the formatted transaction; perform one or operations on the formatted transaction based on the first transaction category to form a reformatted transaction in a format that is recognizable by the remote endpoint; and place the reformatted transaction in a queue for transmission to the remote endpoint.Type: ApplicationFiled: February 16, 2022Publication date: August 10, 2023Inventors: Dimitrios Syrivelis, Paraskevas Bakopoulos, Ioannis (Giannis) Patronas, Elad Mentovich, James Stephen Fields, JR., Haggai Eran, Liran Liss
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Patent number: 11693804Abstract: A computerized system for efficient interaction between a host, the host having a first operating system, and a second operating system, the system comprising a subsystem on the second operating system which extracts data, directly from a buffer which is local to the host, wherein the system is operative for mapping memory from one bus associated with the first operating system to a different bus, associated with the second operating system and from which different bus the memory is accessed, thereby to emulate a connection between the first and second operating systems by cross-bus memory mapping.Type: GrantFiled: June 3, 2021Date of Patent: July 4, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Alex Rosenbaum, Oren Duer, Alexander Mikheev, Nitzan Carmi, Haggai Eran
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Publication number: 20230099304Abstract: In one embodiment, a system includes a peripheral device including a memory access interface to receive from a host device headers of packets, while corresponding payloads of the packets are stored in a host memory of the host device, and descriptors being indicative of respective locations in the host memory at which the corresponding payloads are stored, a data processing unit memory to store the received headers and the descriptors without the payloads of the packets, and a data processing unit to process the received headers, wherein the peripheral device is configured, upon completion of the processing of the received headers by the data processing unit, to fetch the payloads of the packets over the memory access interface from the respective locations in the host memory responsively to respective ones of the descriptors, and packet processing circuitry to receive the headers and payloads of the packets, and process the packets.Type: ApplicationFiled: September 29, 2021Publication date: March 30, 2023Inventors: Haggai Eran, Liran Liss, Yuval Shpigelman, Idan Burstein
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Publication number: 20220391341Abstract: A computerized system for efficient interaction between a host, the host having a first operating system, and a second operating system, the system comprising a subsystem on the second operating system which extracts data, directly from a buffer which is local to the host, wherein the system is operative for mapping memory from one bus associated with the first operating system to a different bus, associated with the second operating system and from which different bus the memory is accessed, thereby to emulate a connection between the first and second operating systems by cross-bus memory mapping.Type: ApplicationFiled: June 3, 2021Publication date: December 8, 2022Inventors: Alex Rosenbaum, Oren Duer, Alexander Mikheev, Nitzan Carmi, Haggai Eran
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Patent number: 11418454Abstract: Apparatus including a first interface to a host processor, a second interface to transmit and receive data packets having headers and payloads, to and from a packet communication network, a memory holding context information regarding a flow of the data and assigning serial numbers to the data packets in the flow, according to a session-layer protocol, and processing circuitry between the first and second interfaces and having acceleration logic, to decode the data records according to the session-layer protocol, using and updating the context information based on the serial numbers and the data records of the received packets, and processing circuitry writing the decoded data records through the first interface to a host memory. The acceleration logic, upon receiving in a given flow a data packet containing a serial number that is out of order, reconstructs the context information and applies that context information in decoding data records in subsequent data packets in the flow.Type: GrantFiled: March 18, 2021Date of Patent: August 16, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Boris Pismenny, Liran Liss, Ilya Lesokhin, Haggai Eran, Adi Menachem
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Patent number: 11184439Abstract: A network node includes a bus switching element, and a network adapter, an accelerator and a host, all coupled to communicate via the bus switching element. The network adapter is configured to communicate with remote nodes over a communication network. The host is configured to establish a RDMA link between the accelerator and the RDMA endpoint by creating a Queue Pair (QP) to be used by the accelerator for communication with the RDMA endpoint via the RDMA link. The accelerator is configured to exchange data, via the network adapter, between a memory of the accelerator and a memory of the RDMA endpoint.Type: GrantFiled: March 24, 2020Date of Patent: November 23, 2021Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Haggai Eran, Dotan David Levi, Maxim Fudim, Liran Liss
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Publication number: 20210203610Abstract: Apparatus including a first interface to a host processor, a second interface to transmit and receive data packets having headers and payloads, to and from a packet communication network, a memory holding context information regarding a flow of the data and assigning serial numbers to the data packets in the flow, according to a session-layer protocol, and processing circuitry between the first and second interfaces and having acceleration logic, to decode the data records according to the session-layer protocol, using and updating the context information based on the serial numbers and the data records of the received packets, and processing circuitry writing the decoded data records through the first interface to a host memory. The acceleration logic, upon receiving in a given flow a data packet containing a serial number that is out of order, reconstructs the context information and applies that context information in decoding data records in subsequent data packets in the flow.Type: ApplicationFiled: March 18, 2021Publication date: July 1, 2021Inventors: Boris Pismenny, Liran Liss, Ilya Lesokhin, Haggai Eran, Adi Menachem
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Patent number: 11005771Abstract: Packet processing apparatus includes a first interface coupled to a host processor and a second interface configured to transmit and receive data packets to and from a packet communication network. A memory holds context information with respect to one or more flows of the data packets conveyed between the host processor and the network in accordance with a reliable transport protocol and with respect to encoding, in accordance with a session-layer protocol, of data records that are conveyed in the payloads of the data packets in the one or more flows. Processing circuitry, coupled between the first and second interfaces, transmits and receives the data packets and includes acceleration logic, which encodes and decodes the data records in accordance with the session-layer protocol using the context information while updating the context information in accordance with the serial numbers and the data records of the transmitted data packets.Type: GrantFiled: October 15, 2018Date of Patent: May 11, 2021Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Boris Pismenny, Liran Liss, Ilya Lesokhin, Haggai Eran, Adi Menachem
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Patent number: 10841243Abstract: A network interface controller that is connected to a host and a packet communications network. The network interface controller includes electrical circuitry configured as a packet processing pipeline with a plurality of stages. It is determined in the network interface controller that at least a portion of the stages of the pipeline are acceleration-defined stages. Packets are processed in the pipeline by transmitting data to an accelerator from the acceleration-defined stages, performing respective acceleration tasks on the transmitted data in the accelerator, and returning processed data from the accelerator to receiving stages of the pipeline.Type: GrantFiled: June 20, 2018Date of Patent: November 17, 2020Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan Levi, Liran Liss, Haggai Eran, Noam Bloch, Idan Burstein, Lior Narkis, Avraham Ganor
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Publication number: 20200314181Abstract: A network node includes a bus switching element, and a network adapter, an accelerator and a host, all coupled to communicate via the bus switching element. The network adapter is configured to communicate with remote nodes over a communication network. The host is configured to establish a RDMA link between the accelerator and the RDMA endpoint by creating a Queue Pair (QP) to be used by the accelerator for communication with the RDMA endpoint via the RDMA link. The accelerator is configured to exchange data, via the network adapter, between a memory of the accelerator and a memory of the RDMA endpoint.Type: ApplicationFiled: March 24, 2020Publication date: October 1, 2020Inventors: Haggai Eran, Dotan David Levi, Maxim Fudim, Liran Liss
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Publication number: 20190140979Abstract: A network interface controller that is connected to a host and a packet communications network. The network interface controller includes electrical circuitry configured as a packet processing pipeline with a plurality of stages. It is determined in the network interface controller that at least a portion of the stages of the pipeline are acceleration-defined stages. Packets are processed in the pipeline by transmitting data to an accelerator from the acceleration-defined stages, performing respective acceleration tasks on the transmitted data in the accelerator, and returning processed data from the accelerator to receiving stages of the pipeline.Type: ApplicationFiled: June 20, 2018Publication date: May 9, 2019Inventors: Dotan Levi, Liran Liss, Haggai Eran, Noam Bloch, Idan Burstein, Lior Narkis, Avraham Ganor
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Publication number: 20190116127Abstract: Packet processing apparatus includes a first interface coupled to a host processor and a second interface configured to transmit and receive data packets to and from a packet communication network. A memory holds context information with respect to one or more flows of the data packets conveyed between the host processor and the network in accordance with a reliable transport protocol and with respect to encoding, in accordance with a session-layer protocol, of data records that are conveyed in the payloads of the data packets in the one or more flows. Processing circuitry, coupled between the first and second interfaces, transmits and receives the data packets and includes acceleration logic, which encodes and decodes the data records in accordance with the session-layer protocol using the context information while updating the context information in accordance with the serial numbers and the data records of the transmitted data packets.Type: ApplicationFiled: October 15, 2018Publication date: April 18, 2019Inventors: Boris Pismenny, Liran Liss, Ilya Lesokhin, Haggai Eran, Adi Menachem
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Patent number: 10218645Abstract: A method in a network node that includes a host and an accelerator, includes holding a work queue that stores work elements, a notifications queue that stores notifications of the work elements, and control indices for adding and removing the work elements and the notifications to and from the work queue and the notifications queue, respectively. The notifications queue resides on the accelerator, and at least some of the control indices reside on the host. Messages are exchanged between a network and the network node using the work queue, the notifications queue and the control indices.Type: GrantFiled: April 8, 2014Date of Patent: February 26, 2019Assignee: Mellanox Technologies, Ltd.Inventors: Shachar Raindel, Yaniv Saar, Haggai Eran, Yishai Israel Hadas, Ari Zigler
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Patent number: 9639464Abstract: A method for data transfer includes receiving in an operating system of a host computer an instruction initiated by a user application running on the host processor identifying a page of virtual memory of the host computer that is to be used in receiving data in a message that is to be transmitted over a network to the host computer but has not yet been received by the host computer. In response to the instruction, the page is loaded into the memory, and upon receiving the message, the data are written to the loaded page.Type: GrantFiled: September 27, 2012Date of Patent: May 2, 2017Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Haggai Eran, Shachar Raindel, Liran Liss, Noam Bloch