Patents by Inventor Hagit Margolin

Hagit Margolin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8499139
    Abstract: An apparatus having a processor and a circuit is disclosed. The processor generally has a pipeline. The circuit may be configured to (i) detect a first write instruction in the pipeline that writes to a resource, (ii) stall a read instruction in the pipeline where (a) a first read-after-write conflict exists between the first write instruction and the read instruction and (b) no other write instruction to the resource is scheduled between the first write instruction and the read instruction and (iii) not stall the read instruction due to the first read-after-write conflict where a second write instruction to the resource is scheduled between the first write instruction and the read instruction.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: July 30, 2013
    Assignee: LSI Corporation
    Inventors: Leonid Dubrovin, Alexander Rabinovitch, Hagit Margolin, Noam Abda
  • Patent number: 8352714
    Abstract: A processor (e.g., a Digital Signal Processor (DSP) core) rewinds a pipeline of instructions upon a watchpoint event in an instruction being processed. The program execution ceases at the instruction in which the watchpoint event occurred, while the instruction and subsequent instructions are cancelled, keeping the hardware components associated with executing the program in their previous states, prior to the watchpoint. The rewind is such that the program is refetched to enable execution to continue from the instruction in which the watchpoint event occurred. The watchpoint event is executed in a “break before make” manner.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: January 8, 2013
    Assignee: LSI Corporation
    Inventors: Eran Dosh, Hagit Margolin, Assaf Rachlevski
  • Publication number: 20120042152
    Abstract: An apparatus having a processor and a circuit is disclosed. The processor generally has a pipeline. The circuit may be configured to (i) detect a first write instruction in the pipeline that writes to a resource, (ii) stall a read instruction in the pipeline where (a) a first read-after-write conflict exists between the first write instruction and the read instruction and (b) no other write instruction to the resource is scheduled between the first write instruction and the read instruction and (iii) not stall the read instruction due to the first read-after-write conflict where a second write instruction to the resource is scheduled between the first write instruction and the read instruction.
    Type: Application
    Filed: August 12, 2010
    Publication date: February 16, 2012
    Inventors: Leonid Dubrovin, Alexander Rabinovitch, Hagit Margolin, Noam Abda
  • Publication number: 20110185156
    Abstract: A processor (e.g., a Digital Signal Processor (DSP) core) rewinds a pipeline of instructions upon a watchpoint event in an instruction being processed. The program execution ceases at the instruction in which the watchpoint event occurred, while the instruction and subsequent instructions are cancelled, keeping the hardware components associated with executing the program in their previous states, prior to the watchpoint. The rewind is such that the program is refetched to enable execution to continue from the instruction in which the watchpoint event occurred. The watchpoint event is executed in a “break before make” manner.
    Type: Application
    Filed: January 28, 2010
    Publication date: July 28, 2011
    Applicant: LSI CORPORATION
    Inventors: Eran Dosh, Hagit Margolin, Assaf Rachlevski