Patents by Inventor HaiBiao YAO

HaiBiao YAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for manufacturing a semiconductor device
    Patent number: 8513075
    Abstract: A manufacturing method for manufacturing a semiconductor device includes depositing a spacer material on a semiconductor substrate, the substrate includes an NMOS region and a PMOS region, each region has a gate formed thereon. The method further includes covering the NMOS region with a first mask, forming a spacer for the PMOS gate by etching the spacer material, forming a recess in the PMOS region by etching, and growing SiGe or SiGe with in-situ-doped B in the recess of the PMOS region to form a PMOS source/drain region. The method further includes performing an anisotropic wet etching on the recess. After growing SiGE or SiGe with in-situ-doped B, the method further includes covering the PMOS region with a second mask and forming a spacer for the NMOS gate by etching the spacer material. The spacer for the PMOS and NMOS gate has a different critical dimension.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: August 20, 2013
    Assignee: Semiconductor Manufacturing International Corporation
    Inventors: Yonggen He, Jingang Wu, Haibiao Yao
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20130032887
    Abstract: A manufacturing method for manufacturing a semiconductor device includes depositing a spacer material on a semiconductor substrate, the substrate includes an NMOS region and a PMOS region, each region has a gate formed thereon. The method further includes covering the NMOS region with a first mask, forming a spacer for the PMOS gate by etching the spacer material, forming a recess in the PMOS region by etching, and growing SiGe or SiGe with in-situ-doped B in the recess of the PMOS region to form a PMOS source/drain region. The method further includes performing an anisotropic wet etching on the recess. After growing SiGE or SiGe with in-situ-doped B, the method further includes covering the PMOS region with a second mask and forming a spacer for the NMOS gate by etching the spacer material. The spacer for the PMOS and NMOS gate has a different critical dimension.
    Type: Application
    Filed: November 29, 2011
    Publication date: February 7, 2013
    Applicant: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Yonggen HE, Jingang WU, HaiBiao YAO