Abstract: Systems, methods, and apparatus for automated close-loop electromagnetic (EM) datalink testing are disclosed. In some embodiments, the disclosed method involves routing, by a user simulator, at least one user input data and at least one user control command to a controller. The method further involves encrypting, by an encryption device(s), at least one user input data to generate at least one encrypted user input data. Also, the method involves transmitting, by a first radio, at least one encrypted user input data to a second radio via an EM signal(s); and receiving, by the second radio, at least one received encrypted user input data. Additionally, the method involves decrypting, by the encryption device(s), at least one received encrypted user input data to produce at least one received user input data. Further, the method involves processing, by the user simulator, at least one received user input data to generate a status report.

Abstract: Systems, methods, and apparatus for automated close-loop electromagnetic (EM) datalink testing are disclosed. In some embodiments, the disclosed method involves routing, by a user simulator, at least one user input data and at least one user control command to a controller. The method further involves encrypting, by an encryption device(s), at least one user input data to generate at least one encrypted user input data. Also, the method involves transmitting, by a first radio, at least one encrypted user input data to a second radio via an EM signal(s); and receiving, by the second radio, at least one received encrypted user input data. Additionally, the method involves decrypting, by the encryption device(s), at least one received encrypted user input data to produce at least one received user input data. Further, the method involves processing, by the user simulator, at least one received user input data to generate a status report.

Abstract: A frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, row addressing decoding apparatus and column address decoding apparatus for selecting memory cells positioned in the array, apparatus for transferring a row address to the row addressing decoding apparatus upon the assertion of a row address strobe signal, apparatus for transferring a column address to the column address decoding apparatus for decoding upon the assertion of a first column address strobe signal, apparatus for latching a column address and any data necessary to complete the access during the first column address strobe signal, apparatus for accessing the particular column the address of which has been latched during the latching of a next subsequent address of a column to be accessed along with any data necessary to complete the next access during the next subsequent column address strobe signal following the first column address strobe signal.

Abstract: A frame buffer having a memory array, circuitry for accessing the array, a plurality of color value registers for storing a plurality of color values which may be written to the array, and circuitry for writing to the memory cells a data representing a single pixel, for writing simultaneously to the memory cells data representing a number of pixels equal to the number of conductors on the data bus, or for writing simultaneously to the memory cells data representing an entire row of pixels of the array.

Abstract: A frame buffer designed to be coupled to a data bus and to an output display in a computer system, the frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, address decoding apparatus for controlling access to the array, the address decoding apparatus including column address decoding apparatus for selecting groups of adjacent columns of the array, a plurality of apparatus for selectively writing to each of the columns of any of said groups of adjacent columns, a plurality of color value registers, latching apparatus for storing pixel data equivalent to a row of pixel data to be displayed on the output display, apparatus for writing pixel data from selected groups of adjacent columns of the array to the latching apparatus, and apparatus for connecting either selected ones of the color value registers, the latches, or the data bus to the apparatus for selectively writing to each of the columns of any of said groups of adjacent columns.

Abstract: A frame buffer including an array of memory cells, circuitry for accessing the memory cells to derive selected pixel data, and output circuitry for providing data signals at an output port, the output circuitry including circuitry for determining the precise time required for a data signal to rise and fall at the output port, such circuitry being selected to provide the minimum delay between succeeding data signals at the output port.

Abstract: A frame buffer including a plurality of array planes of memory cells, row decoding circuitry for selecting rows of memory cells in each of the array planes to be accessed, column decoding circuitry for selecting columns of memory cells in each of the array planes to be accessed, a plurality of bitlines associated with the columns of memory cells of each array plane, each of the bitlines connecting to a column of memory cells and including a bitline sensing amplifier and a column select switch for providing access to the memory cells of that column of the array plane, a plurality of output sense amplifiers adapted to be connected to a selected number of bitlines in an array plane by closing of particular ones of the column select switches in the bitlines, first apparatus for providing output signals from the plurality of output sense amplifiers associated with each array plane to a data bus, and second apparatus for providing output signals from the plurality of output sense amplifiers associated with each arr