Patents by Inventor Hai Dang
Hai Dang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11991937Abstract: A semiconductor device includes a bottom electrode, a top electrode over the bottom electrode, a switching layer between the bottom electrode and the top electrode, wherein the switching layer is configured to store data, a capping layer in contact with the switching layer, wherein the capping layer is configured to extract active metal ions from the switching layer, an ion reservoir region formed in the capping layer, a diffusion barrier layer between the bottom electrode and the switching layer, wherein the diffusion barrier layer includes palladium (Pd), cobalt (Co), or a combination thereof and is configured to obstruct diffusion of the active metal ions between the switching layer and the bottom electrode, and the diffusion layer has a concaved top surface, and a passivation layer covering a portion of the top electrode, and wherein the passivation layer directly contacts a top surface of the switching layer.Type: GrantFiled: June 14, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hai-Dang Trinh, Hsing-Lien Lin, Fa-Shen Jiang
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Publication number: 20240138272Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure over a substrate. A data storage structure overlies the first conductive structure. The data storage structure comprises a first dielectric layer on the first conductive structure and a second dielectric layer on the first dielectric layer. The first dielectric layer comprises a dielectric material and a first dopant having a concentration that changes from a top surface of the first dielectric layer in a direction towards the first conductive structure. A second conductive structure overlies the data storage structure.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang, Bi-Shen Lee
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Patent number: 11967611Abstract: A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of AxB1-xO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.Type: GrantFiled: May 30, 2022Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hai-Dang Trinh, Yi Yang Wei, Fa-Shen Jiang, Bi-Shen Lee, Hsun-Chung Kuang
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Patent number: 11961545Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.Type: GrantFiled: December 7, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fa-Shen Jiang, Hsia-Wei Chen, Hsun-Chung Kuang, Hai-Dang Trinh, Cheng-Yuan Tsai
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Patent number: 11963468Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnects and a diffusion barrier layer on the bottom electrode. The diffusion barrier layer has an inner upper surface that is arranged laterally between and vertically below an outer upper surface of the diffusion barrier film. The outer upper surface wraps around the inner upper surface in a top-view of the diffusion barrier layer. A data storage structure is separated from the bottom electrode by the diffusion barrier layer. A top electrode is arranged over the data storage structure.Type: GrantFiled: July 27, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Fa-Shen Jiang
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Publication number: 20240094076Abstract: The invention relates to an explosive mass drop test device. Specifically, the present invention relates to a method of designing an explosive block drop test device to serve the explosion test process and meet the requirements for ensuring safety during the test. The present invention gives an example of a test device for dropping explosive masses in the range 50-300 kg. In addition, the structure is designed to be simple, easy to integrate and disassemble with the explosive block, the manipulation of dropped objects is simplified. The product of the present invention can be used to test the safety of explosive blocks.Type: ApplicationFiled: August 31, 2023Publication date: March 21, 2024Applicant: VIETTEL GROUPInventors: XUAN BANG DINH, VAN LOI NGUYEN, TAN HAI DANG
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Publication number: 20240099022Abstract: Various embodiments of the present application are directed toward an integrated chip (IC). The IC comprises a dielectric structure disposed over a substrate. A phase change material (PCM) structure is disposed over the dielectric structure. A first conductive structure and a second conductive structure are disposed over and electrically coupled to the PCM structure. A heating structure is disposed in the dielectric structure and laterally between the first conductive structure and the second conductive structure. The heating structure has a first surface and a second surface opposite the first surface. The first surface faces the PCM structure. The first surface has a first width and the second surface has a second width that is greater than the first width.Type: ApplicationFiled: January 3, 2023Publication date: March 21, 2024Inventors: Hai-Dang Trinh, Fu-Ting Sung
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THRESHOLD VOLTAGE-MODULATED MEMORY DEVICE USING VARIABLE-CAPACITANCE AND METHODS OF FORMING THE SAME
Publication number: 20240074217Abstract: A memory device includes a field effect transistor and a variable-capacitance capacitor. A gate structure includes a gate dielectric and an intermediate electrode. The variable-capacitance capacitor includes a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable-capacitance node dielectric and including an electrical-field-programmable metal oxide material. The electrical-field-programmable metal oxide material provides a variable effective dielectric constant, and a data bit may be stored as a dielectric state of the variable-capacitance node dielectric in the memory device. The variable-capacitance node dielectric provides reversible electrical field-dependent resistivity modulation, or reversible electrical field-dependent movement of metal atoms therein.Type: ApplicationFiled: November 10, 2023Publication date: February 29, 2024Inventors: Fa-Shen JIANG, Hsia-Wei CHEN, Hai-Dang TRINH, Hsun-Chung KUANG -
Patent number: 11916127Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.Type: GrantFiled: June 16, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi Yang Wei, Bi-Shen Lee, Hsin-Yu Lai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
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Publication number: 20240064998Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.Type: ApplicationFiled: November 3, 2023Publication date: February 22, 2024Inventors: Bi-Shen Lee, Yi Yang Wei, Hsing-Lien Lin, Hsun-Chung Kuang, Cheng-Yuan Tsai, Hai-Dang Trinh
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Patent number: 11895933Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a bottom electrode over a substrate. A first switching layer is formed on the bottom electrode. The first switching layer comprises a dielectric material doped with a first dopant. A second switching layer is formed over the first switching layer. An atomic percentage of the first dopant in the second switching layer is less than an atomic percentage of the first dopant in the first switching layer. A top electrode is formed over the second switching layer.Type: GrantFiled: June 30, 2022Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang, Bi-Shen Lee
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Publication number: 20240023344Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a lower electrode structure disposed over one or more interconnects. The one or more interconnects are arranged within a lower inter-level dielectric (ILD) structure over a substrate. A barrier is arranged along a lower surface of the lower electrode structure. The barrier separates the lower electrode structure from the one or more interconnects. An amorphous initiation layer is over the lower electrode layer and a ferroelectric material is on the amorphous initiation layer. The ferroelectric material has a substantially uniform orthorhombic crystalline phase. An upper electrode is over the ferroelectric material.Type: ApplicationFiled: July 26, 2023Publication date: January 18, 2024Inventors: Bi-Shen Lee, Yi Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
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Publication number: 20240021700Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.Type: ApplicationFiled: August 8, 2023Publication date: January 18, 2024Inventors: Yi Yang Wei, Bi-Shen Lee, Hsin-Yu Lai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
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Publication number: 20230420493Abstract: A metal-insulator-metal (MIM) capacitor and methods of forming the same are described. In some embodiments, the method includes forming an opening having a first depth in one or more dielectric layers, depositing a layer in the opening and on the one or more dielectric layers, performing an anisotropic etch process to remove portions of the layer formed on horizontal surfaces, extending the opening to a second depth in the one or more dielectric layers, removing the layer, extending the opening to a third depth in the one or more dielectric layers, and forming a MIM capacitor in the opening.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Inventors: Hsing-Lien LIN, Hai-Dang TRINH, Yao-Wen CHANG, Jui-Lin CHU, Cheng-Te LEE
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Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same
Patent number: 11856801Abstract: A memory device includes a field effect transistor and a variable-capacitance capacitor. A gate structure includes a gate dielectric and an intermediate electrode. The variable-capacitance capacitor includes a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable-capacitance node dielectric and including an electrical-field-programmable metal oxide material. The electrical-field-programmable metal oxide material provides a variable effective dielectric constant, and a data bit may be stored as a dielectric state of the variable-capacitance node dielectric in the memory device. The variable-capacitance node dielectric provides reversible electrical field-dependent resistivity modulation, or reversible electrical field-dependent movement of metal atoms therein.Type: GrantFiled: April 12, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Fa-Shen Jiang, Hsia-Wei Chen, Hai-Dang Trinh, Hsun-Chung Kuang -
Publication number: 20230413696Abstract: Some embodiments relate to a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage layer is formed on the bottom electrode. A diffusion barrier layer is formed over the data storage layer. The diffusion barrier layer has a first diffusion activation temperature. A top electrode is formed over the diffusion barrier layer. The top electrode has a second diffusion activation temperature less than the first diffusion activation temperature.Type: ApplicationFiled: July 31, 2023Publication date: December 21, 2023Inventors: Albert Zhong, Cheng-Yuan Tsai, Hai-Dang Trinh, Shing-Chyang Pan
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Publication number: 20230402487Abstract: A Deep Trench Isolation (DTI) structure is disclosed. The DTI structures according to embodiments of the present disclosure include a composite passivation layer. In some embodiments, the composite passivation layer includes a hole accumulation layer and a defect repairing layer. The defect repairing layer is disposed between the hole accumulation layer and a semiconductor substrate in which the DTI structure is formed. The defect repairing layer reduces lattice defects in the interface, thus, reducing the density of interface trap (DIT) at the interface. Reduced density of interface trap facilitates strong hole accumulation, thus increasing the flat band voltage. In some embodiments, the hole accumulation layer according to the present disclosure is enhanced by an oxidization treatment.Type: ApplicationFiled: June 13, 2022Publication date: December 14, 2023Inventors: Bi-Shen LEE, Chia-Wei HU, Hai-Dang TRINH, Min-Ying TSAI, Ching I LI, Hsun-Chung KUANG, Cheng-Yuan TSAI
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Patent number: 11844226Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.Type: GrantFiled: August 9, 2022Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bi-Shen Lee, Yi Yang Wei, Hsing-Lien Lin, Hsun-Chung Kuang, Cheng-Yuan Tsai, Hai-Dang Trinh
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Publication number: 20230387190Abstract: A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of AxB1?xO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.Type: ApplicationFiled: May 30, 2022Publication date: November 30, 2023Inventors: HAI-DANG TRINH, YI YANG WEI, FA-SHEN JIANG, BI-SHEN LEE, HSUN-CHUNG KUANG
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Publication number: 20230389453Abstract: A semiconductor device structure is provided. The structure includes a substrate and a data storage element over the substrate. The structure also includes a protective element extending into the data storage element. A bottom surface of the protective element is between a top surface of the data storage element and a bottom surface of the data storage element. The structure further includes a first electrode electrically connected to the data storage element and a second electrode electrically connected to the data storage element.Type: ApplicationFiled: July 25, 2023Publication date: November 30, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hai-Dang TRINH, Hsing-Lien LIN, Cheng-Yuan TSAI