Abstract: Disclosed is a permanent magnet direct-drive slurry pump based on gas film drag reduction, which includes a permanent magnet motor, a main shaft, an impeller, and a valve block. The permanent magnet motor includes a housing, a stator core, stator windings, a rotor core, and a permanent magnet. The rotor core and the impeller share the main shaft, and an airflow channel is provided inside the main shaft. The impeller includes a front cover plate, a back cover plate, and blades. The blades are modularly manufactured, and blade gas jet holes and hemispherical pits are provided on the pressure surface. The airflow channel in the main shaft is communicated with the blade gas-jet holes. The valve block is disposed at the tail end of the main shaft so as to control gas exhaust and prevent liquid from entering the shaft. The present invention has such advantages as a small size, high efficiency, and strong wear resistance.

Abstract: Disclosed is a permanent magnet direct-drive slurry pump based on gas film drag reduction, which includes a permanent magnet motor, a main shaft, an impeller, and a valve block. The permanent magnet motor includes a housing, a stator core, stator windings, a rotor core, and a permanent magnet. The rotor core and the impeller share the main shaft, and an airflow channel is provided inside the main shaft. The impeller includes a front cover plate, a back cover plate, and blades. The blades are modularly manufactured, and blade gas jet holes and hemispherical pits are provided on the pressure surface. The airflow channel in the main shaft is communicated with the blade gas-jet holes. The valve block is disposed at the tail end of the main shaft so as to control gas exhaust and prevent liquid from entering the shaft. The present invention has such advantages as a small size, high efficiency, and strong wear resistance.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The image sensor includes: a semiconductor substrate; a first active region located on the semiconductor substrate; a doped semiconductor layer located on the first active region; and a contact located on the semiconductor layer, where the first active region includes: a first doped region and a second doped region abutting against the first doped region, wherein the second doped region is located at an upper surface of the first active region, and wherein the second doped region is formed by dopants in the semiconductor layer that are annealed to be diffused to a surface layer of the first doped region. The present disclosure may reduce leakage current and improve device performances.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The method includes: providing a semiconductor structure, where the semiconductor structure includes: a semiconductor substrate, and a first active region located on the semiconductor substrate, the first active region including a first doped region and a second doped region abutting against the first doped region, and the second doped region being located at an upper surface of the first active region; forming a semiconductor layer on an upper surface of the second doped region; and forming a contact connected to the semiconductor layer. The present disclosure enables defects or damages caused when forming the contact to be kept away from a junction field formed by the second doped region and the first doped region. Therefore, leakage current may be reduced and device performances may be improved.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The image sensor includes: a semiconductor substrate; a first active region located on the semiconductor substrate; a doped semiconductor layer located on the first active region; and a contact located on the semiconductor layer, where the first active region includes: a first doped region and a second doped region abutting against the first doped region, wherein the second doped region is located at an upper surface of the first active region, and wherein the second doped region is formed by dopants in the semiconductor layer that are annealed to be diffused to a surface layer of the first doped region. The present disclosure may reduce leakage current and improve device performances.

Abstract: A method of fabricating a spiral inductor includes providing a substrate having a top surface and a bottom surface, forming a plurality of through holes aligned in a vertical plane and spaced apart from each other, forming a metal interconnect structure having at least one top metal layer on the top surface of the substrate, the metal interconnect structure configured to connect to a top portion of the through holes, and forming a redistribution layer having at least a bottom layer on the bottom surface of the substrate. The redistribution layer is configured to connect to a bottom portion of the through holes to form a spiral structure.

Abstract: TSV layout structure and TSV interconnect structure, and their fabrication methods are provided. An exemplary TSV interconnect structure includes a semiconductor substrate having a first region and a second region; and a plurality of through-holes disposed in the first region and the second region of the semiconductor substrate. An average through-hole density of the first region is greater than an average through-hole density of the entire semiconductor substrate. The average through-hole density of the entire semiconductor substrate is less than or equal to about 2%. A metal layer having a planarized surface is filled in the plurality of through-holes in the semiconductor substrate.

Abstract: A method of fabricating a spiral inductor includes providing a substrate having a top surface and a bottom surface, forming a plurality of through holes aligned in a vertical plane and spaced apart from each other, forming a metal interconnect structure having at least one top metal layer on the top surface of the substrate, the metal interconnect structure configured to connect to a top portion of the through holes, and forming a redistribution layer having at least a bottom layer on the bottom surface of the substrate. The redistribution layer is configured to connect to a bottom portion of the through holes to form a spiral structure.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The image sensor includes: a semiconductor substrate; a first active region located on the semiconductor substrate; a doped semiconductor layer located on the first active region; and a contact located on the semiconductor layer, where the first active region includes: a first doped region and a second doped region abutting against the first doped region, wherein the second doped region is located at an upper surface of the first active region, and wherein the second doped region is formed by dopants in the semiconductor layer that are annealed to be diffused to a surface layer of the first doped region. The present disclosure may reduce leakage current and improve device performances.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses an image sensor and a manufacturing method therefor. The method includes: providing a semiconductor structure, where the semiconductor structure includes: a semiconductor substrate, and a first active region located on the semiconductor substrate, the first active region including a first doped region and a second doped region abutting against the first doped region, and the second doped region being located at an upper surface of the first active region; forming a semiconductor layer on an upper surface of the second doped region; and forming a contact connected to the semiconductor layer. The present disclosure enables defects or damages caused when forming the contact to be kept away from a junction field formed by the second doped region and the first doped region. Therefore, leakage current may be reduced and device performances may be improved.

Abstract: A spiral inductor formed in a vertical plane relative to a planar surface of a substrate includes a plurality of through holes disposed in the vertical plane and spaced apart from each other, a metal interconnect structure on the top surface, and a redistribution layer on the bottom surface and having at least one bottom metal layer. The metal interconnect structure and the redistribution layer are connected to each other through the plurality of through holes to form the vertical spiral inductor. The thus formed vertical spiral inductor has a significantly reduced surface area comparing with lateral spiral inductors.

Abstract: An image sensor device includes a top substrate and a subassembly. The top substrate includes a plurality of connection pillars, and the subassembly includes a plurality of connection pads. The connection pillars on the top substrate are bonded to the connection pads in the subassembly. The connection pillars are formed of a first metal and the connection pads are formed of a second metal.

Abstract: An image sensor device includes a top substrate and a subassembly. The top substrate includes a plurality of connection pillars, and the subassembly includes a plurality of connection pads. The connection pillars on the top substrate are bonded to the connection pads in the subassembly. The connection pillars are formed of a first metal and the connection pads are formed of a second metal.

Abstract: A spiral inductor formed in a vertical plane relative to a planar surface of a substrate includes a plurality of through holes disposed in the vertical plane and spaced apart from each other, a metal interconnect structure on the top surface, and a redistribution layer on the bottom surface and having at least one bottom metal layer. The metal interconnect structure and the redistribution layer are connected to each other through the plurality of through holes to form the vertical spiral inductor. The thus formed vertical spiral inductor has a significantly reduced surface area comparing with lateral spiral inductors.

Abstract: TSV layout structure and TSV interconnect structure, and their fabrication methods are provided. An exemplary TSV interconnect structure includes a semiconductor substrate having a first region and a second region; and a plurality of through-holes disposed in the first region and the second region of the semiconductor substrate. An average through-hole density of the first region is greater than an average through-hole density of the entire semiconductor substrate. The average through-hole density of the entire semiconductor substrate is less than or equal to about 2%. A metal layer having a planarized surface is filled in the plurality of through-holes in the semiconductor substrate.

Abstract: This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost.

Abstract: This invention disclosed a novel manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that an oxide-nitride-oxide (ONO) sandwich structure is employed instead of oxide-nitride dual layer structure before trench etching. Another aspect is, through the formation of silicon oxide spacer in trench sidewall and silicon oxide remaining in trench bottom in the deposition and etch back process, the new structure hard mask can effectively protect active region from impurity implanted in ion implantation process.

Abstract: This invention disclosed a kind of electrode pick up structure in shallow trench isolation process. The active region is isolated by shallow trench. A pseudo-buried layer under the bottom of shallow trench is formed. The pseudo-buried layer extends into active region and connects to doping region one which needs to be picked up by an electrode. The pick up is realized by deep trench contacts which etch through STI and get in touch with pseudo buried layer. This invention can reduce the device size, pick up electrode resistance, collector parasitic capacitance, and increase device cut off frequency.

Abstract: This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost.

Abstract: This invention disclosed a kind of electrode picking up structure in LOCOS isolation process. The active region is isolated by local oxide of silicon (LOCOS). A pseudo buried layer under the bottom of LOCOS is formed. The pseudo-buried layer extends into active region and connects to doping region one which needs to be picked up by an electrode. This is achieved by deep trench contacts which etch through LOCOS and get in touch with pseudo buried layer. This invention can reduce the device size, pick up electrode resistance, collector parasitic capacitance, and increase device cut off frequency.