Abstract: An encapsulated semiconductor package includes a substrate including a chip mounting area and inner contact pads on its upper surface and at least two semiconductor chips, each having an active surface with a plurality of chip contact pads and a passive surface. A first semiconductor chip is mounted on the chip mounting area. A spacer block including a first and a second mounting face lying in essentially parallel planes is positioned between and attached to the first semiconductor chip and a second semiconductor chip. The mounting faces of the spacer block have a rounded outline.

Abstract: A substrate includes a number of protruding contact elements. An electrical circuit with electrical contact elements is provided on the substrate. A layer of substrate adhesive is provided on the substrate, the substrate adhesive being in contact with the substrate, with the electrical circuit and with the protruding contact elements. Wiring elements are connected between the protruding contact elements and the electrical contact elements.

Abstract: To avoid air pockets (voids), for example when embedding semiconductor devices (15) in a plastic package molding compound, process parameters in transfer and compression molding are to be contemporaneously controlled. For this purpose, the tendency for voids to form is observed on the basis of test structures in control cavities (7), which form outwardly directed continuations of the mold cavity (3) of a capillary nature.