Patents by Inventor Hai H. Tan

Hai H. Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Closed-loop adaptive voltage scaling for integrated circuits
    Patent number: 9158319
    Abstract: In one embodiment, an integrated circuit (IC) device includes a first logic block having performance characteristics, a first critical path monitor (CPM) configured to monitor the performance characteristics of the first logic block, and a first CPM envelope circuit enveloping the first CPM. The first logic block is configured to operate in at least one of a first functional mode and a first scan mode. The first CPM is adapted to operate in at least one of a second functional mode and a second scan mode. The first and second functional modes use higher clock frequencies, respectively, than the first and second scan modes. The first CPM envelope circuit comprises a clock-gate circuit adapted to allow the IC device to operate in a mixed mode, wherein the first CPM operates in the second functional mode while the first logic block operates in the first scan mode.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: October 13, 2015
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Manjunatha Gowda, Ramnath Venkatraman, Thai M. Nguyen, Hai H. Tan, Prasad Subbarao
  • CLOSED-LOOP ADAPTIVE VOLTAGE SCALING FOR INTEGRATED CIRCUITS
    Publication number: 20150109052
    Abstract: In one embodiment, an integrated circuit (IC) device includes a first logic block having performance characteristics, a first critical path monitor (CPM) configured to monitor the performance characteristics of the first logic block, and a first CPM envelope circuit enveloping the first CPM. The first logic block is configured to operate in at least one of a first functional mode and a first scan mode. The first CPM is adapted to operate in at least one of a second functional mode and a second scan mode. The first and second functional modes use higher clock frequencies, respectively, than the first and second scan modes. The first CPM envelope circuit comprises a clock-gate circuit adapted to allow the IC device to operate in a mixed mode, wherein the first CPM operates in the second functional mode while the first logic block operates in the first scan mode.
    Type: Application
    Filed: November 25, 2013
    Publication date: April 23, 2015
    Applicant: LSI Corporation
    Inventors: Manjunatha Gowda, Ramnath Venkatraman, Thai M. Nguyen, Hai H. Tan, Prasad Subbarao