Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnects and a diffusion barrier layer on the bottom electrode. The diffusion barrier layer has an inner upper surface that is arranged laterally between and vertically below an outer upper surface of the diffusion barrier film. The outer upper surface wraps around the inner upper surface in a top-view of the diffusion barrier layer. A data storage structure is separated from the bottom electrode by the diffusion barrier layer. A top electrode is arranged over the data storage structure.

Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.

Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.

Abstract: Methods and apparatus relating to data streaming accelerators are described. In an embodiment, a hardware accelerator such as a Data Streaming Accelerator (DSA) logic circuitry performs data movement and/or data transformation for data to be transferred between a processor (having one or more processor cores) and a storage device. Other embodiments are also disclosed and claimed.

Abstract: A method of controlling a sensorless motor (32). The method contains the steps of determining a current speed of the motor (32); selectively using a first method, a second method, or a third method to determine a position of a rotor of the motor (32), depending on the current speed of the motor (32); and transmitting a drive signal to the motor (32) based on the determined position of the rotor. A sensorless motor assembly is also disclosed. According to the method, multiple rotor position detection methods are provided to the sensorless motor (32) which cover a full speed range of the motor (32).

Abstract: An adaptive anti-aging sensor based on a cuckoo algorithm, comprising a control module, a reference voltage-controlled oscillator, two shaping circuits, a frequency difference circuit, a resolution adjustment circuit, a 16-bit counter, a parallel-to-serial circuit, an adaptive module, and a digital-to-analog converter. A lookup table is prestored in the adaptive module; when aging monitoring is performed on a voltage-controlled oscillator in an integrated circuit, the adaptive module uses the cuckoo algorithm to determines the optimal working voltage of the currently monitored voltage-controlled oscillator, and the control module accordingly changes the input voltage of the voltage-controlled oscillator of the integrated circuit.

Abstract: The subject invention pertains to an evaporation strategy combined with low-molecular-weight polyacrylic acid (LPAA) to generate an antibacterial dental enamel-like structure. Polystyrene (PS) plates can be used as a removable substrate for the continuous growth of fluorapatite (FAP). The FAP-LPAA composition can be used to kill microorganisms. The LPAA contained dental enamel-like FAP provides an alternative to prevent secondary caries if a carious cavity is filled with shaped dental enamel-like FAP-LPAA.

Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.

Abstract: An adaptive anti-aging sensor based on a cuckoo algorithm, comprising a control module, a reference voltage-controlled oscillator, two shaping circuits, a frequency difference circuit, a resolution adjustment circuit, a 16-bit counter, a parallel-to-serial circuit, an adaptive module, and a digital-to-analog converter. A lookup table is prestored in the adaptive module; when aging monitoring is performed on a voltage-controlled oscillator in an integrated circuit, the adaptive module uses the cuckoo algorithm to determines the optimal working voltage of the currently monitored voltage-controlled oscillator, and the control module accordingly changes the input voltage of the voltage-controlled oscillator of the integrated circuit.

Abstract: Methods and apparatus relating to data streaming accelerators are described. In an embodiment, a hardware accelerator such as a Data Streaming Accelerator (DSA) logic circuitry provides high-performance data movement and/or data transformation for data to be transferred between a processor (having one or more processor cores) and a storage device. Other embodiments are also disclosed and claimed.

Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a redistribution layer, a semiconductor die, conducting connectors, dummy bumps and an underfill. The semiconductor die is disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer. The conducting connectors are disposed between the semiconductor die and the redistribution layer, and are physically and electrically connected with the semiconductor die and the redistribution layer. The dummy bumps are disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die. The underfill is disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die. The dummy bumps are electrically floating. The dummy bumps are in contact with the underfill without contacting the semiconductor die.

Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.

Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.

Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.

Abstract: In accordance with an example embodiment of the present invention, a method comprises allocating a control channel resource in a wireless relay transmission frame on a wireless relay link; generating a control signaling based on at least one of a resource allocation scheme, a status of the wireless relay link and a traffic condition of the wireless relay link; mapping the control signaling to the allocated control channel resource via at least one of a time-first mapping, a frequency-first mapping, and a multiplexing mapping; and transmitting the control signaling in the allocated control channel resource on the wireless relay link to at least one associated relay node.

Abstract: In accordance with an example embodiment of the present invention, a method comprises allocating a control channel resource in a wireless relay transmission frame on a wireless relay link; generating a control signaling based on at least one of a resource allocation scheme, a status of the wireless relay link and a traffic condition of the wireless relay link; mapping the control signaling to the allocated control channel resource via at least one of a time-first mapping, a frequency-first mapping, and a multiplexing mapping; and transmitting the control signaling in the allocated control channel resource on the wireless relay link to at least one associated relay node.

Abstract: An embodiment method includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymer material on the encapsulant. The method further includes planarizing the polymer material and forming a metallization pattern on the polymer material. The metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die.

Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.

Abstract: An integrated fan-out package includes a die, an encapsulant, a redistribution structure, a seed layer, conductive pillars, and a buffer layer. The encapsulant encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure includes dielectric layers and conductive patterns. The dielectric layers are sequentially stacked and the conductive patterns are sandwiched between the dielectric layers. The seed layer and the conductive pillars are sequentially stacked over the redistribution structure. The seed layer is directly in contact with the conductive patterns closest to the conductive pillars. The buffer layer is disposed over the redistribution structure. The dielectric layer closest to the conductive pillars and the buffer layer are sandwiched between the seed layer and the conductive patterns closest to the conductive pillars.