Patents by Inventor Hai-Ming Lee
Hai-Ming Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7960792Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.Type: GrantFiled: November 11, 2010Date of Patent: June 14, 2011Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Publication number: 20110057243Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.Type: ApplicationFiled: November 11, 2010Publication date: March 10, 2011Applicant: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Patent number: 7903472Abstract: An operating method of a non-volatile memory adapted for a non-volatile memory disposed on an SOI substrate including a first conductive type silicon body layer is provided. The non-volatile memory includes a gate, a charge storage structure, a second conductive type drain region, and a second conductive type source region. In operating such a non-volatile memory, voltages are applied to the gate, the second conductive type drain region, the second conductive type source region and the first conductive type silicon body layer beneath the gate, to inject electrons or holes in to the charge storage structure or evacuate the electrons from the charge storage structure by a method selected from a group consisting of channel hot carrier injection, source side injection, band-to-band tunnelling hot carrier injection and Fowler-Nordheim (F-N) tunnelling.Type: GrantFiled: September 24, 2009Date of Patent: March 8, 2011Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Patent number: 7855417Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the conductive type silicon body layer beneath the gate.Type: GrantFiled: August 3, 2007Date of Patent: December 21, 2010Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Patent number: 7682908Abstract: A non-volatile memory including a substrate, a first doped region, a second doped region, a third doped region, a first gate structure, and a second gate structure is disclosed. The doped regions are disposed in the substrate and the second doped region is disposed between the first doped region and the third doped region. The first gate structure is disposed on the substrate between the first doped region and the second doped region. The second gate structure is disposed on the substrate between the second doped region and the third doped region, and comprises a tunneling dielectric layer, a charge trapping structure and a gate from the bottom up.Type: GrantFiled: October 28, 2005Date of Patent: March 23, 2010Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Publication number: 20100014359Abstract: An operating method of a non-volatile memory adapted for a non-volatile memory disposed on an SOI substrate including a first conductive type silicon body layer is provided. The non-volatile memory includes a gate, a charge storage structure, a second conductive type drain region, and a second conductive type source region. In operating such a non-volatile memory, voltages are applied to the gate, the second conductive type drain region, the second conductive type source region and the first conductive type silicon body layer beneath the gate, to inject electrons or holes in to the charge storage structure or evacuate the electrons from the charge storage structure by a method selected from a group consisting of channel hot carrier injection, source side injection, band-to-band tunnelling hot carrier injection and Fowler-Nordheim (F-N) tunnelling.Type: ApplicationFiled: September 24, 2009Publication date: January 21, 2010Applicant: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Publication number: 20080031038Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.Type: ApplicationFiled: August 3, 2007Publication date: February 7, 2008Applicant: EMEMORY TECHNOLOGY INC.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Patent number: 7262457Abstract: A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well and between the first doped region and the second doped region from among the three P-type doped regions. The first gate is formed on the first stacked dielectric layer. The second stacked dielectric layer is formed on the N-type well and between the second doped region and the third doped region from among the three P-type doped regions. The second gate is formed on the second stacked dielectric layer.Type: GrantFiled: December 13, 2004Date of Patent: August 28, 2007Assignee: eMemory Technology Inc.Inventors: Ching-Hsiang Hsu, Shih-Jye Shen, Hsin-Ming Chen, Hai-Ming Lee
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Patent number: 7250654Abstract: A single-poly non-volatile memory device invented to integrate into logic process is disclosed. This non-volatile memory device includes a memory cell unit comprising a PMOS access transistor that is serially connected to a PMOS storage transistor formed in a cell array area, and, in a peripheral circuit area, a high-voltage MOS transistor having a high-voltage gate insulation layer is provided. The PMOS access transistor has an access gate oxide layer that has a thickness equal to the thickness of the high-voltage gate insulation layer in a peripheral circuit area.Type: GrantFiled: November 7, 2005Date of Patent: July 31, 2007Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Publication number: 20070102754Abstract: A single-poly non-volatile memory device invented to integrate into logic process is disclosed. This non-volatile memory device includes a memory cell unit comprising a PMOS access transistor that is serially connected to a PMOS storage transistor formed in a cell array area, and, in a peripheral circuit area, a high-voltage MOS transistor having a high-voltage gate insulation layer is provided. The PMOS access transistor has an access gate oxide layer that has a thickness equal to the thickness of the high-voltage gate insulation layer in a peripheral circuit area.Type: ApplicationFiled: November 7, 2005Publication date: May 10, 2007Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Patent number: 7190623Abstract: A memory cell includes an N-type well, three P-type doped regions formed on the N-type well, a dielectric layer formed on the N-type well and between a first doped region and a second doped region of the three P-type doped regions, a first gate formed on the dielectric layer, a charge storage structure formed on the N-type well and between the second doped region and a third doped region of the three P-type doped regions, and a second gate formed on the charge storage structure. Data is stored in the memory cell by injecting electrons based on the channel-hot-hole induced hot-electron injection mechanism, the band-to-band tunneling induced electron injection mechanism and the Fowler-Nordheim tunneling mechanism. Data is erased from the memory cell by ejecting electrons based on the Fowler-Nordheim tunneling mechanism. Whether data is stored in the charge storage structure or not can be distinguished by read operation.Type: GrantFiled: August 23, 2005Date of Patent: March 13, 2007Assignee: eMemory Technologies Inc.Inventors: Ching-Hsiang Hsu, Shih-Jye Shen, Hsin-Ming Chen, Hai-Ming Lee
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Publication number: 20070045716Abstract: A non-volatile memory including a substrate, a first doped region, a second doped region, a third doped region, a first gate structure, and a second gate structure is disclosed. The doped regions are disposed in the substrate and the second doped region is disposed between the first doped region and the third doped region. The first gate structure is disposed on the substrate between the first doped region and the second doped region. The second gate structure is disposed on the substrate between the second doped region and the third doped region, and comprises a tunneling dielectric layer, a charge trapping structure and a gate from the bottom up.Type: ApplicationFiled: October 28, 2005Publication date: March 1, 2007Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Patent number: 7172940Abstract: A method of fabricating a non-volatile memory based on SONOS is disclosed. By masking the peripheral circuit area with a reverse ONO photoresist layer, the residual ONO layer that is not covered by a gate within the memory array area is etched away to expose the substrate. After the etching of the ONO layer, a channel adjustment doping is carried out subsequently using the reverse ONO photoresist layer as an implant mask, thereby forming lightly doped regions next to the gate within the memory array area. Finally, the reverse ONO photoresist layer is then stripped.Type: GrantFiled: September 15, 2005Date of Patent: February 6, 2007Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Publication number: 20050282332Abstract: A memory cell includes an N-type well, three P-type doped regions formed on the N-type well, a dielectric layer formed on the N-type well and between a first doped region and a second doped region of the three P-type doped regions, a first gate formed on the dielectric layer, a charge storage structure formed on the N-type well and between the second doped region and a third doped region of the three P-type doped regions, and a second gate formed on the charge storage structure. Data is stored in the memory cell by injecting electrons based on the channel-hot-hole induced hot-electron injection mechanism, the band-to-band tunneling induced electron injection mechanism and the Fowler-Nordheim tunneling mechanism. Data is erased from the memory cell by ejecting electrons based on the Fowler-Nordheim tunneling mechanism. Whether data is stored in the charge storage structure or not can be distinguished by read operation.Type: ApplicationFiled: August 23, 2005Publication date: December 22, 2005Inventors: Ching-Hsiang Hsu, Shih-Jye Shen, Hsin-Ming Chen, Hai-Ming Lee
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Patent number: 6975545Abstract: A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well and between the first doped region and the second doped region from among the three P-type doped regions. The first gate is formed on the first stacked dielectric layer. The second stacked dielectric layer is formed on the N-type well and between the second doped region and the third doped region from among the three P-type doped regions. The second gate is formed on the second stacked dielectric layer.Type: GrantFiled: January 5, 2004Date of Patent: December 13, 2005Assignee: eMemory Technology Inc.Inventors: Ching-Hsiang Hsu, Shih-Jye Shen, Hsin-Ming Chen, Hai-Ming Lee
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Publication number: 20050179095Abstract: A memory cell is disclosed. The memory cell includes an N-well, three P-type doped regions formed on the N-type well, a first stacked dielectric layer formed on the N-type well and between a first doped region and a second doped region from among the three P-type doped regions, a first gate formed on the first stacked dielectric layer, a second stacked dielectric layer formed on the N-type well and between the second doped region and a third doped region from among the three P-type doped regions, and a second gate formed on the second stacked dielectric layer.Type: ApplicationFiled: April 28, 2005Publication date: August 18, 2005Inventors: Ching-Hsiang Hsu, Shih-Jye Shen, Hsin-Ming Chen, Hai-Ming Lee
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Patent number: 6922363Abstract: A method for writing a memory module includes providing a plurality of memory cells. Each memory cell includes a substrate, a P-type drain and source, a gate, and a stack dielectric layer which stores 2-bit data. Memory cells are arranged in a matrix with gates and sources on the same row connected respectively to the same word line and same source line, and drains on the same column connected to the same bit line. Each line receives a respective voltage with the word line of the memory cell to be written receiving voltage to turn on its P-type channel, the word line of the memory cell not to be written receiving voltage to turn off its P-type channel, and the bit line of the memory cell to be written receiving voltage so that a hot hole in its P-type channel induces hot electron injection into its stack dielectric layer.Type: GrantFiled: December 22, 2003Date of Patent: July 26, 2005Assignee: eMemory Technology Inc.Inventors: Ching-Hsiang Hsu, Shih-Jye Shen, Hsin-Ming Chen, Hai-Ming Lee
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Publication number: 20050145927Abstract: A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well and between the first doped region and the second doped region from among the three P-type doped regions. The first gate is formed on the first stacked dielectric layer. The second stacked dielectric layer is formed on the N-type well and between the second doped region and the third doped region from among the three P-type doped regions. The second gate is formed on the second stacked dielectric layer.Type: ApplicationFiled: December 13, 2004Publication date: July 7, 2005Inventors: Ching-Hsiang Hsu, Shih-Jye Shen, Hsin-Ming Chen, Hai-Ming Lee
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Publication number: 20050098817Abstract: A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well and between the first doped region and the second doped region from among the three P-type doped regions. The first gate is formed on the first stacked dielectric layer. The second stacked dielectric layer is formed on the N-type well and between the second doped region and the third doped region from among the three P-type doped regions. The second gate is formed on the second stacked dielectric layer.Type: ApplicationFiled: January 5, 2004Publication date: May 12, 2005Inventors: Ching-Hsiang Hsu, Shih-Jye Shen, Hsin-Ming Chen, Hai-Ming Lee
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Publication number: 20050030793Abstract: A method for writing a memory module includes providing a plurality of memory cells. Each memory cell includes a substrate, a P-type drain and source, a gate, and a stack dielectric layer which stores 2-bit data. Memory cells are arranged in a matrix with gates and sources on the same row connected respectively to the same word line and same source line, and drains on the same column connected to the same bit line. Each line receives a respective voltage with the word line of the memory cell to be written receiving voltage to turn on its P-type channel, the word line of the memory cell not to be written receiving voltage to turn off its P-type channel, and the bit line of the memory cell to be written receiving voltage so that a hot hole in its P-type channel induces hot electron injection into its stack dielectric layer.Type: ApplicationFiled: December 22, 2003Publication date: February 10, 2005Inventors: Ching-Hsiang Hsu, Shih-Jye Shen, Hsin-Ming Chen, Hai-Ming Lee