Abstract: A system for generating an advanced surround view for a vehicle includes a plurality of cameras to generate image data. Sensors are configured to determine kinematic data of the vehicle. Kinematic data are also obtained by a visual odometry module and/or a deep-vision mechanism. A processor is configured to process image data captured by the plurality of cameras to generate a 360-degree surround view layer representative of a surrounding area. The processor is further configured to construct an improved bicycle kinematic model for processing kinematic data to generate an under-chassis layer representative of an area under the vehicle. The processor is further configured to generate a 3D vehicle model layer and overlay objects layer. Display screens display a GUI of combined scene of the 360-degree surround view layer, under-chassis layer, 3D vehicle model layer and overlay objects layer as would be viewed from a virtual camera viewpoint.

Abstract: A sampling method and a data recovery circuit using the same are provided. The sampling method includes following steps. First, a first strobe, a second strobe, a third strobe, and a fourth strobe are provided, wherein the second strobe lags the first strobe a first predetermined phase, the third and the fourth strobe respectively lag the first and the second strobe a second predetermined phase, and the second predetermined phase is half of the first predetermined phase. Then, a digital signal is respectively sampled with the first and the second strobe. Thereafter, the positions of data transition points of the digital signal are determined according to the sampling results of the first and the second strobe. Next, the third or the fourth strobe is selected as a preferable sampling strobe according to the determination result. Finally, the digital signal is sampled with the preferable sampling strobe.

Abstract: A sampling method and a data recovery circuit using the same are provided. The sampling method includes following steps. First, a first strobe, a second strobe, a third strobe, and a fourth strobe are provided, wherein the second strobe lags the first strobe a first predetermined phase, the third and the fourth strobe respectively lag the first and the second strobe a second predetermined phase, and the second predetermined phase is half of the first predetermined phase. Then, a digital signal is respectively sampled with the first and the second strobe. Thereafter, the positions of data transition points of the digital signal are determined according to the sampling results of the first and the second strobe. Next, the third or the fourth strobe is selected as a preferable sampling strobe according to the determination result. Finally, the digital signal is sampled with the preferable sampling strobe.

Abstract: A low-voltage differential signal driver with a pre-emphasis circuit having a current control circuit and a pre-emphasis circuit is provided. Wherein, the pre-emphasis circuit includes the current sourcing circuit and the current sinking circuit, both of which have similar circuit structure, coupled to the current control circuit, respectively. The current sourcing circuit and the current sinking circuit are controlled by two sets of driving signals, so that the pre-emphasis circuit provides an extra driving current to the current control circuit at an instant when the current control circuit switches the current direction. In addition, each set of driving signals contains two synchronous but phase-inversed driving signals. The time it takes for the current steering circuit to switch terminated resistor current between upward and downward directions is decreased.

Abstract: A digital-to-analog converter has a plurality of current cells. Each of the current cells has a level shifter and a current source. The level shifter connects to a first power terminal and a second power terminal to convert a first input signal and a second input signal into a first output signal and a second output signal. The current source has two cascaded MOS transistors connected to the first power terminal in series, a first MOS switch having a gate for receiving the first output signal, and a second MOS switch having a gate for receiving the second output signal. A voltage level of the first power terminal is greater than a voltage level of the second power terminal. When one of the current cells operates, one of the first MOS switch and the second MOS switch of the current source is turned on and operates in a saturation region.

Abstract: A digital-to-analog converter has a plurality of current cells. Each of the current cells has a level shifter and a current source. The level shifter connects to a first power terminal and a second power terminal to convert a first input signal and a second input signal into a first output signal and a second output signal. The current source has two cascaded MOS transistors connected to the first power terminal in series, a first MOS switch having a gate for receiving the first output signal, and a second MOS switch having a gate for receiving the second output signal. A voltage level of the first power terminal is greater than a voltage level of the second power terminal. When one of the current cells operates, one of the first MOS stitch and the second MOS switch of the current source is turned on and operates in a saturation region.

Abstract: An adaptive equalizer system and method uses an averaging algorithm to adjust equalization and amplitude for a data signal. Two sampled data points, spanning a sampling window, are obtained from the equalized signal. The data points are evaluated to determine when a signal condition persists long enough to require equalization adjustment, as well as evaluating persistent conditions in the amplitude of the received data signal. By monitoring persistent conditions in the equalized signal, the average signal received by the equalizer is compensated. The bit resolution of the equalizer control and the amplitude control can be selected for a desired resolution in a system. The incoming data signal is used to generate the requisite timing signals for sampling and control such that high frequency clock circuits and PLL techniques are unnecessary resulting in lower power consumption and reduced costs.

Abstract: An input signal with an associated pulse width can be sampled using a sampling method that does not require a clock signal. The input signal is compared to a reference level signal to produce a comparator output signal. Strobe signals are generated from the input signal, where the strobe signals occur within a pulse width of the input signal. Sampled data points are generated in response to the comparator output signal and the strobe signals such that the sampled data points are within the pulse-width of the input signal. One of the strobe signals may be used to periodically reset the comparator. The sampling logic circuit may be constructed from common logic gates and memory circuits such as flip-flops. In one example application the sampling method is applied to an equalizer system. The equalizer system includes an equalizer circuit that produces an equalized signal. A data slicer circuit converts the equalized signal into a digital representation.