Abstract: A method for compensating for bit line delays in semiconductor memories including the steps of developing a dummy word line signal representative of the delay of a word line of a semiconductor memory and controlling the sense amplifier of the semiconductor memory with a control signal derived, at least in part, from the dummy word line signal. Preferably, the dummy word line signal is delayed by a fixed delay or by delay produced by a proportionally loaded dummy bit line. A circuit embodying the method of the present invention includes a dummy word which produces a dummy word signal upon the activation of any word of the semiconductor memory and a delay coupling the dummy word signal to the clock input of the sense amplifier. The delay may be a fixed delay including a number of logic elements, or it may be developed by a proportionally loaded bit line which has a fraction of the load of an actual bit line of the semiconductor memory.