Patents by Inventor Hai-Won Kim
Hai-Won Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240371701Abstract: A method for forming a semiconductor device may include forming, on a substrate, a trench which delimits a preliminary active region. A buffer layer may be formed on the preliminary active region using a first heat treatment process that is performed at 520° C. to 580° C. A sacrificial layer may be formed by replacing the buffer layer. An active region may be exposed by removing the sacrificial layer. A semiconductor liner may be formed on the active region.Type: ApplicationFiled: September 13, 2023Publication date: November 7, 2024Inventors: Bong Seok JEON, Ji Yong KIM, Hai Won KIM, Jeong Hyun LEE
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Publication number: 20230403855Abstract: A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.Type: ApplicationFiled: August 9, 2023Publication date: December 14, 2023Applicant: SK hynix Inc.Inventors: In-Su PARK, Jong-Gi KIM, Hai-Won KIM, Hoe-Min JEONG
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Patent number: 11751395Abstract: A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.Type: GrantFiled: January 3, 2022Date of Patent: September 5, 2023Assignee: SK hynix Inc.Inventors: In-Su Park, Jong-Gi Kim, Hai-Won Kim, Hoe-Min Jeong
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Publication number: 20220123020Abstract: A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.Type: ApplicationFiled: January 3, 2022Publication date: April 21, 2022Applicant: SK hynix Inc.Inventors: In-Su PARK, Jong-Gi KIM, Hai-Won KIM, Hoe-Min JEONG
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Patent number: 11244956Abstract: A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.Type: GrantFiled: November 11, 2019Date of Patent: February 8, 2022Assignee: SK hynix Inc.Inventors: In-Su Park, Jong-Gi Kim, Hai-Won Kim, Hoe-Min Jeong
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Publication number: 20200328226Abstract: A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.Type: ApplicationFiled: November 11, 2019Publication date: October 15, 2020Applicant: SK hynix Inc.Inventors: In-Su PARK, Jong-Gi KIM, Hai-Won KIM, Hoe-Min JEONG
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Patent number: 10006121Abstract: Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer.Type: GrantFiled: February 25, 2014Date of Patent: June 26, 2018Assignee: EUGENE TECHNOLOGY CO., LTD.Inventors: Sung Kil Cho, Hai Won Kim, Sang Ho Woo, Seung Woo Shin, Gil Sun Jang, Wan Suk Oh
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Publication number: 20180105951Abstract: Provided is an equipment for manufacturing a semiconductor. The equipment for manufacturing a semiconductor includes a cleaning chamber in which a cleaning process is performed on substrates, an epitaxial chamber in which an epitaxial process for forming an epitaxial layer on each of the substrates is performed, and a transfer chamber to which the cleaning chamber and the epitaxial chamber are connected to sides surfaces thereof, the transfer chamber including a substrate handler for transferring the substrates, on which the cleaning process is completed, into the epitaxial chamber. The cleaning chamber is performed in a batch type with respect to the plurality of substrates.Type: ApplicationFiled: December 14, 2017Publication date: April 19, 2018Applicant: EUGENE TECHNOLOGY CO., LTD.Inventors: Young Dae KIM, Jun-Jin HYON, Sang Ho WOO, Seung Woo SHIN, Hai Won KIM
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Patent number: 9818604Abstract: Provided is a method of depositing an insulation layer on a trench in a substrate, in which the trench having an aspect ratio of 5:1 or more is formed, including: an insulation layer deposition step of performing an adsorption step of adsorbing silicon to the substrate by injecting a silicon precursor into the inside of a chamber into which the substrate is loaded, a first purge step of removing the unreacted silicon precursor and reaction byproducts from the inside of the chamber, a reaction step of forming the adsorbed silicon as an insulation layer including silicon by supplying a first reaction source to the inside of the chamber, and a second purge step of removing the unreacted first reaction source and reaction byproducts from the inside of the chamber; and a densification step of forming a plasma atmosphere in the inside of the chamber by applying an radio frequency (RF) power and densifying the insulation layer including silicon by using the plasma atmosphere, wherein a frequency of the RF power is iType: GrantFiled: June 16, 2015Date of Patent: November 14, 2017Assignee: EUGENE TECHNOLOGY CO., LTD.Inventors: Hai-Won Kim, Chang-Hun Shin, Seok-Yun Kim, Choon-Sik Jeong
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Patent number: 9761473Abstract: Provided are a substrate supporting unit and a substrate processing apparatus, and a method of manufacturing the substrate supporting unit. The substrate supporting unit includes a susceptor on which a substrate is placed on a top surface thereof, one or more heat absorbing members which are capable of being converted between a mounted position at which the heat absorbing member is disposed on an upper portion of the susceptor to thermally contact the susceptor and a released position at which the heat absorbing member is separated from the upper portion of the susceptor, the one or more heat absorbing members absorbing heat of the susceptor at the mounted position, and an edge ring having a plurality of fixing slots in which the heat absorbing members are selectively inserted and fixed.Type: GrantFiled: August 24, 2012Date of Patent: September 12, 2017Assignee: EUGENE TECHNOLOGY CO., LTD.Inventors: Hai Won Kim, Sung-Kil Cho
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Publication number: 20170256410Abstract: Provided is a method and apparatus for depositing an amorphous silicon film. The method includes supplying a source gas and an atmospheric gas onto a substrate in a state where the substrate is loaded in a chamber to deposit the amorphous silicon film on the substrate. The atmospheric gas includes at least one of hydrogen and helium. The source gas includes at least one of silane (SiH2), disilane (Si2H6), and dichlorosilane (SiCl2H2).Type: ApplicationFiled: May 18, 2017Publication date: September 7, 2017Applicant: EUGENE TECHNOLOGY CO., LTD.Inventors: Seung-Woo SHIN, Hai-Won KIM, Woo-Duck JUNG, Sung-Kil CHO, Wan-Suk OH, Ho-Min CHOI, Koon-Woo LEE
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Patent number: 9741574Abstract: Provided is a method of cyclically depositing a thin film including: performing an oxide depositing operation of repeatedly performing a deposition operation, a first purge operation, a reaction operation, and a second purge operation, wherein the deposition operation deposits silicon on a target by injecting a silicon precursor into a chamber into which the target is loaded, the first purge operation removes a non-reacted silicon precursor and a reacted byproduct from inside the chamber, the reaction operation supplies a first reaction source including oxygen into the chamber to form the deposited silicon as an oxide including silicon, and the second purge operation removes a non-reacted first reaction source and a reacted byproduct from the inside of the chamber; and performing a plasma processing operation of supplying plasma made of a second reaction source including nitrogen to the inside of the chamber to process the oxide including the silicon.Type: GrantFiled: September 23, 2014Date of Patent: August 22, 2017Assignee: EUGENE TECHNOLOGY CO., LTD.Inventors: Hai-Won Kim, Seok-Yun Kim
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Patent number: 9721798Abstract: Provided is a method and apparatus for depositing an amorphous silicon film. The method includes supplying a source gas and an atmospheric gas onto a substrate in a state where the substrate is loaded in a chamber to deposit the amorphous silicon film on the substrate. The atmospheric gas includes at least one of hydrogen and helium. The source gas includes at least one of silane (SiH2), disilane (Si2H6), and dichlorosilane (SiCl2H2).Type: GrantFiled: September 15, 2014Date of Patent: August 1, 2017Assignee: EUGENE TECHNOLOGY CO., LTD.Inventors: Seung-Woo Shin, Hai-Won Kim, Woo-Duck Jung, Sung-Kil Cho, Wan-Suk Oh, Ho-Min Choi, Koon-Woo Lee
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Publication number: 20170148625Abstract: Provided is a method of depositing an insulation layer on a trench in a substrate, in which the trench having an aspect ratio of 5:1 or more is formed, including: an insulation layer deposition step of performing an adsorption step of adsorbing silicon to the substrate by injecting a silicon precursor into the inside of a chamber into which the substrate is loaded, a first purge step of removing the unreacted silicon precursor and reaction byproducts from the inside of the chamber, a reaction step of forming the adsorbed silicon as an insulation layer including silicon by supplying a first reaction source to the inside of the chamber, and a second purge step of removing the unreacted first reaction source and reaction byproducts from the inside of the chamber; and a densification step of forming a plasma atmosphere in the inside of the chamber by applying an radio frequency (RF) power and densifying the insulation layer including silicon by using the plasma atmosphere, wherein a frequency of the RF power is iType: ApplicationFiled: June 16, 2015Publication date: May 25, 2017Applicant: EUGENE TECHNOLOGY CO., LTD.Inventors: Hai-Won KIM, Chang-Hun SHIN, Seok-Yun KIM, Choon-Sik JEONG
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Publication number: 20160300723Abstract: Provided is a method of cyclically depositing a thin film including: performing an oxide depositing operation of repeatedly performing a deposition operation, a first purge operation, a reaction operation, and a second purge operation, wherein the deposition operation deposits silicon on a target by injecting a silicon precursor into a chamber into which the target is loaded, the first purge operation removes a non-reacted silicon precursor and a reacted byproduct from inside the chamber, the reaction operation supplies a first reaction source including oxygen into the chamber to form the deposited silicon as an oxide including silicon, and the second purge operation removes a non-reacted first reaction source and a reacted byproduct from the inside of the chamber; and performing a plasma processing operation of supplying plasma made of a second reaction source including nitrogen to the inside of the chamber to process the oxide including the silicon.Type: ApplicationFiled: September 23, 2014Publication date: October 13, 2016Applicant: EUGENE TECHNOLOGYCO., LTD.Inventors: Hai-Won KIM, Seok-Yun KIM
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Patent number: 9425057Abstract: A method for manufacturing a memory device having a vertical structure according to one embodiment of the present invention comprises: a step for alternatingly laminating one or more insulation layers and one or more sacrificial layers on a substrate; a step for forming a penetration hole for penetrating the insulation layer and the sacrificial layer; a step for forming a pattern for filling up the penetration hole; a step for forming an opening for penetrating the insulation layer and the sacrificial layer; and a step for removing the sacrificial layer by supplying an etchant through the opening, wherein the step for laminating the insulation layer includes a step for depositing a first silicon oxide film by supplying to the substrate at least one gas selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and the step for laminating the sacrificial layer includes a step for depositing a second silicon oxide film by supplying dichlorosilane (SiCl2H2) to the substrate.Type: GrantFiled: October 6, 2011Date of Patent: August 23, 2016Assignee: Eugene Technology Co., Ltd.Inventors: Sung Kil Cho, Hai Won Kim, Sang Ho Woo, Seung Woo Shin, Gil Sun Jang, Wan Suk Oh
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Publication number: 20160211141Abstract: Provided is a method and apparatus for depositing an amorphous silicon film. The method includes supplying a source gas and an atmospheric gas onto a substrate in a state where the substrate is loaded in a chamber to deposit the amorphous silicon film on the substrate. The atmospheric gas includes at least one of hydrogen and helium. The source gas includes at least one of silane (SiH2), disilane (Si2H6), and dichlorosilane (SiCl2H2).Type: ApplicationFiled: September 15, 2014Publication date: July 21, 2016Applicant: EUGENE TECHNOLOGY CO., LTD.Inventors: Seung-Woo SHIN, Hai-Won KIM, Woo-Duck JUNG, Sung-Kil CHO, Wan-Suk OH, Ho-Min CHOI, Koon-Woo LEE
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Patent number: 9396954Abstract: Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer.Type: GrantFiled: October 6, 2011Date of Patent: July 19, 2016Assignee: EUGENE TECHNOLOGY CO., LTD.Inventors: Sung Kil Cho, Hai Won Kim, Sang Ho Woo, Seung Woo Shin, Gil Sun Jang, Wan Suk Oh
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Patent number: 9312125Abstract: A cyclic deposition method for thin film formation includes forming a silicon thin film on an object by injecting a silicon precursor into a chamber in which the object is loaded, depositing silicon on the object, and performing a first purge, removing an unreacted portion of the silicon precursor and reaction by-products from the interior of the chamber, pre-processing a surface of the silicon thin film by forming a plasma atmosphere in the chamber and supplying a first reaction source having a hydrogen atom, and forming the silicon thin film as an insulating film including silicon, by forming the plasma atmosphere in the chamber and supplying a second reaction source having one or more oxygen atoms, one or more nitrogen atoms, or a mixture thereof.Type: GrantFiled: December 23, 2014Date of Patent: April 12, 2016Assignee: Eugene Technology Co., Ltd.Inventors: Hai-Won Kim, Seok-Yun Kim, Chang-Hun Shin, Jeong-Hoon Lee
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Publication number: 20150187560Abstract: A cyclic deposition method for thin film formation includes forming a silicon thin film on an object by injecting a silicon precursor into a chamber in which the object is loaded, depositing silicon on the object, and performing a first purge, removing an unreacted portion of the silicon precursor and reaction by-products from the interior of the chamber, pre-processing a surface of the silicon thin film by forming a plasma atmosphere in the chamber and supplying a first reaction source having a hydrogen atom, and forming the silicon thin film as an insulating film including silicon, by forming the plasma atmosphere in the chamber and supplying a second reaction source having one or more oxygen atoms, one or more nitrogen atoms, or a mixture thereof.Type: ApplicationFiled: December 23, 2014Publication date: July 2, 2015Inventors: Hai-Won Kim, Seok-Yun Kim, Chang-Hun Shin, Jeong-Hoon Lee