Abstract: Disclosed herein is a compound of Formula (I) for inhibiting both Bcl-2 wild type and mutated Bcl-2, in particular, Bcl-2 G101V and D103Y, and a method of using the compound disclosed herein for treating dysregulated apoptotic diseases.

Abstract: Disclosed herein is a compound of Formula (I) for inhibiting Bcl-2 and treating disease associated with undesirable bcl-2 activity (Bcl-2 related diseases), a method of using the compounds disclosed herein for treating dysregulated apoptotic diseases including cancers and treating autoimmune disease, and a pharmaceutical composition comprising the same.

Abstract: Disclosed herein is a compound of Formula (I) for inhibiting Bcl-2 and treating disease associated with undesirable bcl-2 activity (Bcl-2 related diseases), a method of using the compounds disclosed herein for treating dysregulated apoptotic diseases including cancers and treating autoimmune disease, and a pharmaceutical composition comprising the same.

Abstract: Provided are methods and apparatuses for packet scheduling for software-defined networking in an edge computing environment. A packet scheduling method according to an exemplary embodiment of the present disclosure comprises: receiving packets arriving at a queue connected to a switch in a software-defined network in an edge computing environment; moving the packets in the queue forward one position based on the order of arrival each time a packet is served by the switch; and if a new packet enters the switch while the buffer in the queue is full, pushing out the packet at the front and putting the new packet at the end of the queue.

Abstract: Disclosed herein is a compound of Formula (I) for inhibiting Bcl-2 and treating disease associated with undesirable bcl-2 activity (Bcl-2 related diseases), a method of using the compounds disclosed herein for treating dysregulated apoptotic diseases including cancers and treating autoimmune disease, and a pharmaceutical composition comprising the same.

Abstract: Disclosed herein is a compound of Formula (I) for inhibiting Bcl-2 and treating disease associated with undesirable bcl-2 activity (Bcl-2 related diseases), a method of using the compounds disclosed herein for treating dysregulated apoptotic diseases including cancers and treating autoimmune disease, and a pharmaceutical composition comprising the same.

Abstract: Provided are methods and apparatuses for packet scheduling for software-defined networking in an edge computing environment. A packet scheduling method according to an exemplary embodiment of the present disclosure comprises: receiving packets arriving at a queue connected to a switch in a software-defined network in an edge computing environment; moving the packets in the queue forward one position based on the order of arrival each time a packet is served by the switch; and if a new packet enters the switch while the buffer in the queue is full, pushing out the packet at the front and putting the new packet at the end of the queue.

Abstract: Disclosed are a compound, a stereisomer and a tautomer thereof, a pharmaceutically acceptable salt thereof, and a solvate or a prodrug thereof, which can be used for preventing or treating a ROR? mediated disease. The compound has the structural formula (I).

Abstract: Disclosed are a compound, a stereisomer and a tautomer thereof, a pharmaceutically acceptable salt thereof, and a solvate or a prodrug thereof, which can be used for preventing or treating a ROR? mediated disease. The compound has the structural formula (I).

Abstract: A test system for overclocking capability of a central processing unit (CPU) includes a basic input and output system (BIOS), a frequency generator, and a watchdog timer. The BIOS includes an input module, a watchdog control module, and a frequency increasing module. The input module inputs an initial frequency of a CPU to the frequency generator to adjust a real-time frequency of the CPU. The watchdog control module sends a counter signal to the watchdog timer in a preset time interval. The watchdog timer receives the counter signal. If the watchdog timer does not receive the counter signal within the preset time, the watchdog timer outputs a reset signal to restart the computer. The frequency increasing module adds a preset increment to the real-time frequency to obtain a newly adjusted frequency, and provides the newly adjusted frequency to the frequency generator to adjust the real-time frequency.

Abstract: A method for integrating an operating system (OS) into a basic input output system (BIOS) chip and to boot a computer system using an image file stored in a server. A bootable image file of the OS is integrated with a virtual disk program and other BIOS instructions and stored into the BIOS chip. When the computer system is powered up, the OS stored in the BIOS can be booted to allow the another OS stored in the server to be downloaded into the harddisk and executed. The BIOS OS can also allow an OS stored on the local drive to be executed.

Abstract: A method for integrating an operating system (OS) into a basic input output system (BIOS) chip and to boot a computer using programs stored in the BIOS. A bootable image file of the OS is integrated with a virtual disk program and other BIOS instructions and stored into the BIOS chip. When the computer is powered up and upon the condition that an OS in a hard disk of a computer system is damaged, the OS in the BIOS chip is executed.

Abstract: The present invention relates to tetracyclodipyrano-coumarin compounds of general formula (I), wherein the substituents are defined herein. These compounds exihibit dual biological activities of anti human immunodeficiency virus type 1 (HIV-1) infection and anti-Mycobacterium Tuberculosis (TB) infection.

Abstract: A test system for overclocking capability of a central processing unit (CPU) includes a basic input and output system (BIOS), a frequency generator, and a watchdog timer. The BIOS includes an input module, a watchdog control module, and a frequency increasing module. The input module inputs an initial frequency of a CPU to the frequency generator to adjust a real-time frequency of the CPU. The watchdog control module sends a counter signal to the watchdog timer in a preset time interval. The watchdog timer receives the counter signal. If the watchdog timer does not receive the counter signal within the preset time, the watchdog timer outputs a reset signal to restart the computer. The frequency increasing module adds a preset increment to the real-time frequency to obtain a newly adjusted frequency, and provides the newly adjusted frequency to the frequency generator to adjust the real-time frequency.

Abstract: A voltage adjusting system for motherboard components of a computer includes a basic input and output system (BIOS) and a voltage regulator. The BIOS includes an input module, a voltage detection module, and a voltage record module. The input module is for receiving an adjusted voltage of a motherboard component and providing the adjusted voltage to the voltage regulator to adjust a voltage of the motherboard component. The voltage detection module is for determining whether the motherboard component works normally under the adjusted voltage. The voltage record module is for receiving the adjusted voltage and storing the adjusted voltage in a memory system when the motherboard component works normally under the adjusted voltage.

Abstract: A load detecting system includes a chipset connected to a hardware unit and an interrupt controller connected to the chipset. A maximum voltage value and a minimum voltage value of the hardware unit are stored in the chipset. The chipset is configured to detect a voltage signal of the hardware, and compare the voltage signal to the maximum voltage and the minimum voltage values to output an interrupt signal to the interrupt controller correspondingly. The interrupt controller is configured to adjust work frequency of the hardware unit according to the interrupt signal.