Patents by Inventor Haian Lin

Haian Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180204917
    Abstract: A power MOSFET IC device including an array of MOSFET cells formed in a semiconductor substrate. The array of MOSFET cells comprises an interior region of interior MOSFET cells and an outer edge region of peripheral MOSFET cells, each interior MOSFET cell of the interior region of the array comprising a pair of interior MOSFET devices coupled to each other at a common drain contact. In an example embodiment, each interior MOSFET device includes a source contact (SCT) trench extended into a substrate contact region of the semiconductor substrate. The SCT trench is provided with a length less than a linear portion of a polysilicon gate of the interior MOSFET device, wherein the SCT trench is aligned to the polysilicon gate having a curvilinear layout geometry.
    Type: Application
    Filed: May 22, 2017
    Publication date: July 19, 2018
    Inventors: Furen LIN, Frank BAIOCCHI, Haian LIN, Yunlong LIU, Lark LIU, Wei SONG, ZiQiang ZHAO
  • Publication number: 20180130789
    Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.
    Type: Application
    Filed: October 11, 2017
    Publication date: May 10, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: Haian Lin, Frank Baiocchi
  • Publication number: 20180090490
    Abstract: A power MOSFET IC device including a source-down enhancement mode transistor formed in a semiconductor substrate and a depletion mode transistor formed in a doped region of the semiconductor substrate. A gate terminal of the depletion mode transistor is formed over at least a portion of the doped region as a field plate that is switchably connectable to a source terminal of the source-down enhancement mode transistor. A control circuit may be provided to facilitate a connection between the gate terminal of the depletion mode transistor and the source terminal of the source-down enhancement mode transistor when the power MOSFET integrated circuit is in an OFF state. The control circuit may also be configured to facilitate connection of the gate terminal of the depletion mode transistor to a gate terminal of the source-down enhancement mode FET device or to an external driver that provides a reference voltage, when the power MOSFET is in an ON state.
    Type: Application
    Filed: September 23, 2016
    Publication date: March 29, 2018
    Inventors: Haian Lin, Frank Baiocchi
  • Publication number: 20170229435
    Abstract: A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.
    Type: Application
    Filed: February 9, 2016
    Publication date: August 10, 2017
    Inventors: Jonathan Almeria Noquil, Osvaldo Jorge Lopez, Haian Lin
  • Patent number: 9646965
    Abstract: An integrated semiconductor transistor chip for use in a buck converter includes a high side transistor formed on the chip and comprising a laterally diffused metal oxide semiconductor (LDMOS) transistor and a low side transistor formed on the chip and comprising a source down metal oxide semiconductor field effect transistor (MOSFET). The chip also includes a substrate of the chip for use as a source for the low side transistor and an n-doped well for isolation of the high side transistor from the source of the low side transistor.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: May 9, 2017
    Assignee: Texas Instruments Incorporated
    Inventors: Jun Wang, Frank Baiocchi, Haian Lin
  • Publication number: 20150214222
    Abstract: An integrated semiconductor transistor chip for use in a buck converter includes a high side transistor formed on the chip and comprising a laterally diffused metal oxide semiconductor (LDMOS) transistor and a low side transistor formed on the chip and comprising a source down metal oxide semiconductor field effect transistor (MOSFET). The chip also includes a substrate of the chip for use as a source for the low side transistor and an n-doped well for isolation of the high side transistor from the source of the low side transistor.
    Type: Application
    Filed: January 29, 2015
    Publication date: July 30, 2015
    Inventors: Jun WANG, Frank BAIOCCHI, Haian LIN
  • Publication number: 20140183622
    Abstract: A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.
    Type: Application
    Filed: December 20, 2013
    Publication date: July 3, 2014
    Inventors: Haian LIN, Shuming XU, Jacek KOREC
  • Patent number: 8294210
    Abstract: A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: October 23, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Christopher Boguslaw Kocon, John Manning Savidge Neilson, Simon John Molloy, Haian Lin, Charles Walter Pearce, Gary Eugene Daum
  • Patent number: 8288820
    Abstract: A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS transistor with an n-type substrate source. A charge balanced channel diode (CBCD) with an n-type substrate. A process for forming a high performance, power integrated circuit composed of two CBDENMOS transistors formed on an n-substrate. A process for forming a power integrated circuit composed of one CBDENMOS transistor and one CBCD on an n-type substrate.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: October 16, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Christopher Boguslaw Kocon, John Manning Savidge Neilson, Simon John Molloy, Haian Lin, Charles Walter Pearce
  • Publication number: 20110303976
    Abstract: A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming.
    Type: Application
    Filed: June 15, 2010
    Publication date: December 15, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christopher Boguslaw KOCON, John Manning Savidge NEILSON, Simon John MOLLOY, Haian LIN, Charles Walter PEARCE, Gary Eugene DAUM
  • Publication number: 20100315159
    Abstract: A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS transistor with an n-type substrate source. A charge balanced channel diode (CBCD) with an n-type substrate. A process for forming a high performance, power integrated circuit composed of two CBDENMOS transistors formed on an n-substrate. A process for forming a power integrated circuit composed of one CBDENMOS transistor and one CBCD on an n-type substrate.
    Type: Application
    Filed: June 15, 2010
    Publication date: December 16, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christopher Boguslaw Kocon, John Manning Savidge Neilson, Simon John Molloy, Haian Lin, Charles Walter Pearce
  • Publication number: 20060175192
    Abstract: The present invention, referred to as optoelectronic probe, concerns a novel apparatus and method for characterization and micromanipulation of particles or biomolecules in an electrolyte solution. Electric fields, which include both time constant and time-varying components, are applied to a thin insulating layer covered, lightly doped semiconductor material. Illumination injects carriers into the insulator/semiconductor interface to compensate the leaking minority carrier current and maintain an inversion layer, which works as an electrode to control the particle movements. A particle array, or even a single cell, can be assembled in, or moved along with the inversion layer electrode, which is induced by illumination. Furthermore, an impedance analyzer is utilized to characterize the trapped particles, or single cell. The present invention has numerous uses, such as bio-chemical analysis systems, and nanosize structures assembly for electronic or optical devices.
    Type: Application
    Filed: February 9, 2005
    Publication date: August 10, 2006
    Inventor: Haian Lin
  • Patent number: 7088116
    Abstract: The present invention, referred to as optoelectronic probe, concerns a novel apparatus and method for characterization and micromanipulation of particles or biomolecules in an electrolyte solution. Electric fields, which include both time constant and time-varying components, are applied to a thin insulating layer covered, lightly doped semiconductor material. Illumination injects carriers into the insulator/semiconductor interface to compensate the leaking minority carrier current and maintain an inversion layer, which works as an electrode to control the particle movements. A particle array, or even a single cell, can be assembled in, or moved along with the inversion layer electrode, which is induced by illumination. Furthermore, an impedance analyzer is utilized to characterize the trapped particles, or single cell. The present invention has numerous uses, such as bio-chemical analysis systems, and nanosize structures assembly for electronic or optical devices.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: August 8, 2006
    Inventor: Haian Lin