Abstract: A modified para-aramid polymer solution, a coating slurry, a battery separator and preparation methods thereof provided, which belong to the field of lithium battery material. A modified para-aramid polymer solution is prepared, which can be directly used for preparing a coating slurry and for coating a lithium battery separator. The problem that the traditional para-aramid is difficult to dissolve in polar solvents to prepare a coated film is effectively solved; and in the prepared lithium battery separator, ceramic particles are wrapped in the three-dimensional network structure of the modified para-aramid, so that the shortage of powder falling of ceramic particles is effectively improved, and the thermal performance and safe use performance of the lithium battery separator are improved. The present method has obvious advantages of high production efficiency, good product performance, low production cost and the like over the prior art.

Abstract: A method and apparatus for providing a program-based hardware co-simulation of a circuit design are described. In one example, a circuit design is implemented for programmable logic to establish a design under test (DUT). A co-simulation model is programmatically generated using primitives defined by an application programming interface (API). The circuit design is simulated by configuring the programmable logic with the DUT and driving a co-simulation engine to communicate with the DUT via execution of the co-simulation model.

Abstract: A computer-implemented method of creating a simulation engine for simulating a circuit design can include receiving a source code contribution from a high level modeling system and receiving a simulation model specified in an interpretive language that specifies the circuit design. The source code contribution can be compiled together with the simulation model using a Just-In-Time compiler. A simulation engine, specified in native machine code, can be output as a single, integrated software component formed from the source code contribution and the simulation model.

Abstract: Approaches for preparing simulation models of an electronic circuit are disclosed. The design is partitioned into first and second clusters. The design includes a source module in the first cluster connected to a destination module in the second cluster. The first cluster is compiled into a first model for a software-based co-simulation platform for simulating behavior of the source module using the first model. The first cluster and the second cluster of the design are compiled into a second model for a hardware-based co-simulation platform that includes a programmable logic circuit configurable for emulating behavior of the design using the second model. An interconnection block is generated and stored in the second model. The interconnection block is switchable between coupling of the destination module in the second model to the source module of the first model or to a source module of the second model.

Abstract: A computer-implemented method of specifying a circuit design within a high-level modeling system (HLMS) can include, responsive to a scripted user input, instantiating a first and a second block objects within a hardware description interface (HDI) that is communicatively linked with the HLMS and, responsive to instantiating the first and second block objects, creating and displaying, within the HLMS, first and second modeling blocks representing the first and second xBlock objects respectively. Responsive to instantiating, within the HDI, a signal object bound to an output port of the first block object and an input port of the second block object, a modeling line can be created and displayed within the HLMS visually linking an output of the first modeling block with an input of the second modeling block. The first modeling block, second modeling block, and modeling line can be stored as a description of the circuit design.

Abstract: Design synchronization for a High-Level Modeling System (“HLMS”) of an integrated circuit device (“IC”) is described. In a method for generating a netlist, a description of a first circuit block of a user design is input to a programmed computer system programmed with a computer-aided modeling system. The description includes output port information of the first circuit block and synchronization signal information. The computer-aided modeling system selects a circuit core for the first circuit block responsive to output port information and the synchronization signal information, the circuit core including port metadata. The computer-aided modeling system selects at least one macro responsive to the port metadata for generation of the netlist. The macro is for rate synchronized coupling of the first circuit block to a second circuit block of the user design. The computer-aided modeling system outputs the netlist including the macro.

Abstract: Approaches for processing an electronic circuit design. In one embodiment, the graphical model of an outer subsystem block and an inner subsystem block are translated into a high-level language (HLL) program. The HLL program includes a specification of a first function corresponding to the outer subsystem block and within the specification of the first function a specification of a second function corresponding to the inner subsystem block. The specification of the first function references a parameter of the outer subsystem block and specifies invocation of the second function. The specification of the second function specifies invocation of a third function corresponding to a leaf block in the inner subsystem block. The specification of the first function references a variable corresponding to the parameter, and that variable is referenced by the second or third functions. Execution of the HLL program instantiates a model of the design.

Abstract: A computer-implemented method of scheduling a multi-rate, synchronous circuit design for simulation within a high-level modeling system. The method can include determining a component clocking rate for each of a plurality of synchronous components of the circuit design and classifying each of the plurality of synchronous components into a plurality of schedules according to component clocking rate. For each clock cycle during simulation, the method can include selecting one of the plurality of schedules and executing each synchronous component of the selected schedule. A value determined through execution of a synchronous component of the circuit design can be output.

Abstract: Method and apparatus for translating a first program in a dynamically-typed language to a program in a hardware description language. From the dynamically-typed-language first program, a second program in single static assignment format is generated. For cases where a variable is assigned different data types at different places in the program, the assignments of the different data types are resolved for the variable. The second program is then translated to a program in the hardware description language.

Abstract: Method and apparatus for modeling multiple instances of an electronic circuit using an imperative programming language description is described. In one example, a program is defined using an imperative programming language. The program includes multiple calls to a function. The function includes a persistent variable associated with an internal state of the electronic circuit. The function is configured to initialize the persistent variable based on at least one call path to the function in the program.

Abstract: Implementing an electronic design having software-implemented blocks and hardware-implemented blocks. A specification of the electronic design is created in response to selection of blocks from a library, and at least one of the blocks is available for implementation in a selectable one of a software implementation for an embedded processor on a programmable logic device (PLD) and a hardware implementation on the PLD. A specification of each block in a first subset is obtained from the library and translated into an execution function of the software implementation of the block. Peripheral functions are generated for connections between blocks in the first subset and blocks in a second subset, which are designated for a hardware implementation on the PLD. A program is generated that invokes each peripheral function and each execution function in an order determined from the interconnections between the blocks.

Abstract: A method (100) of translating an imperative language function into a parameterized hardware component can include the steps of using (102) formal imperative function arguments to represent at least one among a component input port and a component parameter and distinguishing (104) between formal imperative function arguments intended as component parameters from formal imperative function arguments intended as component input ports. The method can generate (106) hardware description by providing a framework where imperative language functions can be translated into hardware components by being instantiated, combined and simulated. Arbitrary code can be associated (108) to a function-importing block as parameterization code and enabling an assignment of arbitrary code to actual imperative function arguments. The arbitrary code can be executed (110) in an interpreter that analyzes assigned variables by name and compares variable names with the formal argument identifiers in an imported function.

Abstract: Method and apparatus for translating an imperative programming language description of a circuit into a hardware description is described. In one example, a state object in a function of the imperative programming language description is identified. Use of the state object in the function is compared against criteria associated with each of a plurality of hardware objects. The state object is mapped to a hardware object of the plurality of hardware objects such that the use of the state object in the function satisfies the criteria of the hardware object. At least one instance of the hardware object is generated in the hardware description.

Abstract: Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.

Abstract: Method, apparatus, and computer readable medium for simulating an integrated circuit within a modeling system using one or more circuit description language representations of circuitry is described. By example, a circuit description language representation of the one or more circuit description language representations of circuitry is translated into a program language circuit description. A first simulation process is executed and input data is obtained therefrom. A second simulation process is executed with the input data as parametric input to produce output data, the second simulation process being derived from the program language circuit description. The output data produce by the second simulation process is provided to the first simulation process.

Abstract: Method and apparatus for preparing a design in a high-level modeling system. Hardware description language (HDL) code is generated for one or more of a plurality of high-level subsystems in a high-level design tagged by the user for HDL code generation. Previously generated HDL code may be reused instead of generating new HDL code for each subsystem tagged by the user for HDL code reuse.

Abstract: Method and apparatus for creating a circuit design. An object-oriented program instantiates a plurality of objects that model a circuit design. The objects have hierarchy attributes, connectivity attributes, and display attributes that describe a plurality of modules. The hierarchy attributes define parent-child relationships between modules, the connectivity attributes define input-output connections between modules, and the display attributes define a layout of the modules for viewing. Each of the objects has an associated method for generating a design specification in a selected format. When the program is executed, the design specification is generated from the set of objects. Depending on the capabilities of the available tools, the modules and logic elements are displayed in accordance with the display attributes either from the object-oriented program or from the design specification.

Abstract: A method of inlining a function call of a first high level design language (HDL) into a second HDL is disclosed comprising the steps of: (a) translating the function call of the first HDL into a function body file of the second HDL; (b) translating a signature of the function call of the first HDL into a data file including predetermined data of the function signature; and (c) translating the function call of the first HDL into a sequence of macro definitions based on the corresponding data file followed by a compiler directive to include the corresponding function body file of the second HDL. In one embodiment, the first HDL is a VHDL and the second HDL is a Verilog HDL.

Abstract: Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.