Patents by Inventor Haibing ZHAO

Haibing ZHAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10651933
    Abstract: Systems and methods for calibrating a ring modulator are described. A system may include a controller configured to provide a first test signal to the ring modulator, determine a first candidate temperature control signal for a heater of the ring modulator when the first test signal is provided to the ring modulator, determine a first optical swing of an optical signal at a drop port of the ring modulator, determine a second candidate temperature control signal for the heater when the first test signal is provided to the ring modulator, determine a second optical swing of an optical signal at the drop port, select an optimal optical swing from the first optical swing and the second optical swing, and select one of the first candidate temperature control signal or the second candidate temperature control signal based on the optimal optical swing selected.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: May 12, 2020
    Assignee: Xilinx, Inc.
    Inventors: Ping-Chuan Chiang, Kee Hian Tan, Gourav Modi, Nakul Narang, Haibing Zhao, Yohan Frans
  • Patent number: 8928416
    Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: January 6, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Haibing Zhao
  • Publication number: 20120223750
    Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.
    Type: Application
    Filed: February 29, 2012
    Publication date: September 6, 2012
    Inventor: Haibing ZHAO