Patents by Inventor HAIFA HARIRI
HAIFA HARIRI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105575Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core, and a pad over the core, where the pad has a first width. In an embodiment, a surface finish is over the pad, where the surface finish has a second width that is substantially equal to the first width. In an embodiment, the package substrate further comprises a solder resist over the pad, where the solder resist comprises an opening that exposes a portion of the surface finish. In an embodiment, the opening has a third width that is smaller than the second width.Type: ApplicationFiled: September 26, 2022Publication date: March 28, 2024Inventors: Jason M. GAMBA, Haifa HARIRI, Kristof DARMAWIKARTA, Srinivas V. PIETAMBARAM, Hiroki TANAKA, Kyle MCELHINNY, Xiaoying GUO, Steve S. CHO, Ali LEHAF, Haobo CHEN, Bai NIE, Numair AHMED
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Publication number: 20240006298Abstract: An electronic device may include an integrated circuit, for instance a semiconductor die. The electronic device may include a substrate having a first layer and a second layer. The first and second layers may include interconnects recessed below a surface of the substrate. The substrate may include a passivation layer directly coupled with portions of the interconnects. A solder resist material may at least partially cover portions of the passivation layer directly coupled with the first interconnect surface.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Suddhasattwa Nad, Steve Cho, Marcel Arlan Wall, Onur Ozkan, Ali Lehaf, Yi Yang, Jason Scott Steill, Gang Duan, Brandon C. Marin, Jeremy D. Ecton, Srinivas Venkata Ramanuja Pietambaram, Haifa Hariri, Bai Nie, Hiroki Tanaka, Kyle Mcelhinny, Jason Gamba, Venkata Rajesh Saranam, Kristof Darmawikarta, Haobo Chen
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Patent number: 11552019Abstract: Embodiments include semiconductor packages. A semiconductor package includes a first patch and a second patch on an interposer. The semiconductor package also includes a first substrate in the first patch, and a second substrate in the second patch. The semiconductor package further includes an encapsulation layer over and around the first and second patches, a plurality of build-up layers on the first patch, the second patch, and the encapsulation layer, and a plurality of dies and a bridge on the build-up layers. The bridge may be communicatively coupled with the first substrate of the first patch and the second substrate of the second patch. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first and second substrates may be EMIBs and/or high-density packaging (HDP) substrates. The bridge may be positioned between two dies, and over an edge of the first patch and an edge of the second patch.Type: GrantFiled: March 12, 2019Date of Patent: January 10, 2023Assignee: Intel CorporationInventors: Haifa Hariri, Amruthavalli P. Alur, Wei-Lun K. Jen, Islam A. Salama
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Publication number: 20220102055Abstract: Embodiments disclosed herein include electronic packages with embedded inductors and methods of forming such electronic packages. In an embodiment, the electronic package comprises a package core, and a plated through hole (PTH) through a thickness of the package core. In an embodiment, the electronic package further and a magnetic shell around a perimeter of the PTH, where a height of the magnetic shell is less than the thickness of the package core. In an embodiment, the magnetic shell comprises a substantially vertical sidewall and a bottom surface that is tapered.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: Brandon C. MARIN, Krishna BHARATH, Haifa HARIRI, Tarek A. IBRAHIM
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Publication number: 20220093536Abstract: Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.Type: ApplicationFiled: September 23, 2020Publication date: March 24, 2022Inventors: Krishna BHARATH, William J. LAMBERT, Haifa HARIRI, Siddharth KULASEKARAN, Mathew MANUSHAROW, Anne AUGUSTINE
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Patent number: 11222877Abstract: The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.Type: GrantFiled: September 29, 2017Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Omkar Karhade, Robert L. Sankman, Nitin A. Deshpande, Mitul Modi, Thomas J. De Bonis, Robert M. Nickerson, Zhimin Wan, Haifa Hariri, Sri Chaitra J. Chavali, Nazmiye Acikgoz Akbay, Fadi Y. Hafez, Christopher L. Rumer
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Publication number: 20210305138Abstract: Embodiments disclosed herein include electronic packaged assemblies. In an embodiment, an electronic package comprises first and second surfaces. The second surface has a land pad in a land pad opening. The land pad is spaced away from the land pad opening by an outer gap. The land pad is a closed loop. In an embodiment, the electronic package is electrically coupled to a socket. The socket has an interconnect with a first connector and a second connector. The first connector of the interconnect is directly coupled to at least one portion of the closed loop. In an embodiment, when the first connector is coupled to at least two or more portions of the closed loop, the portions are spaced away from each other by a portion of the inner or outer gap. The closed loop comprises a conductive line continuously extending from a first end to a second end.Type: ApplicationFiled: March 24, 2020Publication date: September 30, 2021Inventors: Zhichao ZHANG, Zhenguo JIANG, Haifa HARIRI, Kemal AYGÜN, Sriram SRINIVASAN
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Publication number: 20210273036Abstract: An integrated circuit (IC) package substrate, comprising a magnetic material embedded within a dielectric material. A first surface of the dielectric material is below the magnetic material, and a second surface of the dielectric material, opposite the first surface, is over the magnetic material. A metallization level comprising a first metal feature is embedded within the magnetic material. A second metal feature is at an interface of the magnetic material and the dielectric material. The second metal feature has a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.Type: ApplicationFiled: February 28, 2020Publication date: September 2, 2021Applicant: Intel CorporationInventors: Brandon C. Marin, Tarek Ibrahim, Prithwish Chatterjee, Haifa Hariri, Yikang Deng, Sheng C. Li, Srinivas Pietambaram
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Publication number: 20200294920Abstract: Embodiments include semiconductor packages. A semiconductor package includes a first patch and a second patch on an interposer. The semiconductor package also includes a first substrate in the first patch, and a second substrate in the second patch. The semiconductor package further includes an encapsulation layer over and around the first and second patches, a plurality of build-up layers on the first patch, the second patch, and the encapsulation layer, and a plurality of dies and a bridge on the build-up layers. The bridge may be communicatively coupled with the first substrate of the first patch and the second substrate of the second patch. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first and second substrates may be EMIBs and/or high-density packaging (HDP) substrates. The bridge may be positioned between two dies, and over an edge of the first patch and an edge of the second patch.Type: ApplicationFiled: March 12, 2019Publication date: September 17, 2020Inventors: Haifa HARIRI, Amruthavalli P. ALUR, Wei-Lun K. JEN, Islam A. SALAMA
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Publication number: 20190103385Abstract: The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: Intel CorporationInventors: OMKAR KARHADE, ROBERT L. SANKMAN, NITIN A. DESHPANDE, MITUL MODI, THOMAS J. DE BONIS, ROBERT M. NICKERSON, ZHIMIN WAN, HAIFA HARIRI, SRI CHAITRA J. CHAVALI, NAZMIYE ACIKGOZ AKBAY, FADI Y. HAFEZ, CHRISTOPHER L. RUMER