Abstract: A system and method for real-time transmission of a panoramic video, which propose a new grouping method and bitrate decision method specifically for a panoramic 360-degree video. The grouping method takes into account fields of view of different users, thus effectively reducing the bandwidth consumption of repeated video segments, while ensuring user fairness and making full use of network bandwidth resources when allocating resources. The system and method of the invention can maximize the long-term QoE of users under the condition of limited bandwidth, and avoid the problem that the existing schemes are complex and difficult to meet real-time requirements of users.

Abstract: Provided are a method and an apparatus for rechecking a defective product. The method includes: a display terminal receives sent image information of at least one detection image corresponding to the defective product (S110). The image information includes: an ID of the at least one detection image, and defect information corresponding to the at least one detection image. The defect information includes: a defect type of a defect in the at least one detection image, and defect coordinates of the defect in the at least one detection image. The display terminal displays the at least one detection image that is pre-stored corresponding to the defective product and marks the defect information corresponding to the at least one detection image according to the image information (S120).

Abstract: The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.

Abstract: The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to methods to remove a contact etch stop layer without consuming material of a self-aligned contact (SAC) layer. The method includes: forming a gate structure on a substrate; forming a capping layer on the gate structure; forming a contact etch stop layer of a first material, adjacent to the gate metal structure; converting the contact etch stop layer to a second material which is different than the capping layer; and selectively removing the second material without completely removing the capping layer.

Abstract: Integrated circuits and methods of forming the same are provided herein. In an embodiment, an integrated circuit includes a semiconductor substrate that has an isolated well. A multilayer metallization stack overlies the semiconductor substrate. The multilayer metallization stack includes a metal layer, a functional via, and a dummy metal feature. The metal layer includes a first line in electrical communication with the isolated well through a contact. The functional via is in electrical communication with the first line and the contact. The dummy metal feature is in electrical communication with the functional via.

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

Abstract: A contact etch stop layer includes a nitride layer formed over a sacrificial gate structure and a polysilicon layer formed over the nitride layer. During subsequent processing, the polysilicon layer is adapted to oxidize and form an oxide layer. The oxidation of the polysilicon layer effectively shields the underlying nitride contact etch stop layer from oxidation, which protects the mechanical integrity of the nitride layer.

Abstract: The disclosure is directed to methods of planarizing an integrated circuit structure including: forming a dielectric over a first nitride layer; planarizing the dielectric to a top surface of a set of nitride fins in a first region and removing the dielectric from a second region to expose the substantially planar upper surface in a second region; forming a second nitride layer over the dielectric and the top surface of the set of nitride fins and over the substantially planar upper surface; planarizing the second nitride layer such that the second nitride layer in the second region is planar with the top surface of the dielectric and the set of nitride fins, and such that the second nitride layer is removed from the first region; and performing an etch such that the first nitride layer in the first region is planar with the first nitride layer in the second region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to notched fin structures and methods of manufacture. The structure includes: a fin structure composed of a substrate material and a stack of multiple epitaxially grown materials on the substrate material; a notch formed in a first epitaxially grown material of the stack of multiple epitaxially grown materials of the fin structure; an insulator material within the notch of the fin structure; and an insulator layer surrounding the fin structure and above a surface of the notch.

Abstract: Integrated circuits and methods of forming the same are provided herein. In an embodiment, an integrated circuit includes a semiconductor substrate that has an isolated well. A multilayer metallization stack overlies the semiconductor substrate. The multilayer metallization stack includes a metal layer, a functional via, and a dummy metal feature. The metal layer includes a first line in electrical communication with the isolated well through a contact. The functional via is in electrical communication with the first line and the contact. The dummy metal feature is in electrical communication with the functional via.

Abstract: A method of removing the CESL from small canyon TS structures of a MOSFET device while maintaining gate cap height and the resulting device are provided. Embodiments include providing two gates laterally separated over and perpendicular to a fin of a semiconductor device, each gate having sidewall spacers and a nitride cap; forming a conformal SiN CESL on bottom and side surfaces of a trench formed between opposing spacers between the gates; filling the trench with oxide; planarizing the spacers, nitride caps, oxide, and CESL; removing the oxide; forming a topological flat-SiN layer over the spacers, nitride caps, and CESL; removing the topological flat-SiN layer from side and bottom surfaces of the trench; removing the CESL and the topological flat-SiN layer down to a top surface of the spacers; and performing contact metallization.

Abstract: Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.

Abstract: A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a device well, such as a floating p-type well. After processing, the temporary discharge path is rendered non-function, enabling the device to function properly.

Abstract: Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.

Abstract: Methods of lithographic patterning and structures formed by lithographic patterning. A hardmask layer is formed on a dielectric layer, a feature is formed on the hardmask layer, and a mandrel is formed that extends in a first direction across the first feature. The mandrel and the hardmask layer beneath the mandrel are removed to pattern the hardmask layer with the feature masking a section of the hardmask layer. After the hardmask layer is patterned, the dielectric layer is etched to form a first trench and a second trench that are separated by a section of the dielectric layer masked by the section of the hardmask layer. The first trench and the second trench are filled with a conductor layer to respectively form a first wire and a second wire that is separated from the first wire by the section of the dielectric layer.

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

Abstract: One illustrative method disclosed herein includes forming a liner layer above a layer of spacer material, forming an ion-containing region in at least a portion of a first portion of the liner layer while not forming the ion-containing region in a second portion of the liner layer, performing a liner etching process on the first and second portions of the liner layer so as to remove the second portion of the liner layer while leaving at least a portion of the first portion of the liner layer positioned adjacent a gate structure and, with the first portion of the liner layer positioned adjacent the gate structure, performing at least one spacer formation anisotropic etching process on the layer of spacer material so as to define a spacer adjacent the gate structure.

Abstract: One illustrative method disclosed herein includes, among other things, forming a first sacrificial layer comprising amorphous silicon or polysilicon material around a fin in a lateral space between a plurality of laterally spaced apart gate structures that are positioned around the fin, performing a first selective etching process to remove a first sacrificial layer selectively relative to surrounding material so as to expose the fin in the lateral space, forming an epi material on the exposed portion of the fin, and forming a second layer of a sacrificial material above the epi material. The method also includes selectively removing the second layer of sacrificial material relative to at least the first layer of material to thereby define a source/drain contact opening that exposes the epi material and forming a self-aligned trench conductive source/drain contact structure that is conductively coupled to the epi material.

Abstract: A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a device well, such as a floating p-type well. After processing, the temporary discharge path is rendered non-function, enabling the device to function properly.