Abstract: The present utility model provides an outlet water switching device with temperature display and a shower system, which are applied to an upward water-feeding shower system. The system includes: a body, wherein the body accommodates an inner body, a valve seat and a water guide chamber in mutual communication are formed on the inner body to dispose a switching valve assembly and a hydraulic power generating device, an inlet water opening and at least one outlet water opening are further disposed on the inner body, the inlet water opening is in communication with the water guide chamber, the outlet water openings are in communication with the valve seat respectively, a water flow impacts the hydraulic power generating device disposed in the water guide chamber to enable the hydraulic power generating device to autonomously generate power.

Abstract: The present utility model discloses a wall-concealed faucet, including a box body pre-buried in a wall and a valve body disposed in the box body. A first valve seat and a second valve seat for disposing a regulating valve and a switching valve respectively are formed on the valve body, and inlet water openings two or more outlet water openings for supplying cold water and hot water respectively are disposed on the valve body. The inlet water opening communicates through a water channel in the valve body with the regulating valve disposed on the first valve seat. The regulating valve is in communication with the switching valve disposed in the second valve seat. The regulating valve is used to regulate a water temperature and a flow rate, and the switching valve is used to switch a water delivery state of each outlet water opening.

Abstract: A method for performing an analysis of at least one logic stage in a netlist, which include one or more drivers, is provided. The method includes operations of generating at least one look-up table for an output transient current to be based on values of input and output voltages using data available from a cell library; synthesizing analytically at least one current source model, which includes a DC component and a plurality of parasitic capacitances, using the look-up table; simulating the logic stage using the current source model to model the drivers; and obtaining characteristics of the simulated logic stage. A system and a machine-readable medium for performing the method are also provided.

Abstract: A system and method for estimating propagation noise that is induced by a non-zero noise glitch at the input of the driver circuit. Such propagation noise is a function of both the input noise glitch and the driver output effective capacitive load, which is typically part of the total wiring capacitance due to resistive shielding in deep sub-micron interconnects. The noise-driven effective capacitance solution provided herein also estimates the propagation noise induced by a non-zero noise glitch at the input of the driving gate. Gate propagation noise rules describing a relationship between the output noise properties and the input noise properties and the output loading capacitance are used within the noise-driven effective capacitance process to determine the linear Thevenin model of the driving gate. The linearized Thevenin driver model is then employed to analyze both the propagation noise and the combined coupling and propagation noise typically seen in global signal nets.

Abstract: A method for performing an analysis of at least one logic stage in a netlist, which include one or more drivers, is provided. The method includes operations of generating at least one look-up table for an output transient current to be based on values of input and output voltages using data available from a cell library; synthesizing analytically at least one current source model, which includes a DC component and a plurality of parasitic capacitances, using the look-up table; simulating the logic stage using the current source model to model the drivers; and obtaining characteristics of the simulated logic stage. A system and a machine-readable medium for performing the method are also provided.

Abstract: A system and method for estimating propagation noise that is induced by a non-zero noise glitch at the input of the driver circuit. Such propagation noise is a function of both the input noise glitch and the driver output effective capacitive load, which is typically part of the total wiring capacitance due to resistive shielding in deep sub-micron interconnects. The noise-driven effective capacitance solution provided herein also estimates the propagation noise induced by a non-zero noise glitch at the input of the driving gate. Gate propagation noise rules describing a relationship between the output noise properties and the input noise properties and the output loading capacitance are used within the noise-driven effective capacitance process to determine the linear Thevenin model of the driving gate. The linearized Thevenin driver model is then employed to analyze both the propagation noise and the combined coupling and propagation noise typically seen in global signal nets.

Abstract: A method and system for reducing noise in a power grid of an integrated circuit, which optimizes the placement and sizing of decoupling capacitors in the power grid. Logic cells are located in a first layout of the integrated circuit with empty spaces between the adjacent cells, and the placement of the cells is changed to a second layout wherein the size of the empty spaces between the adjacent cells also change. The decoupling capacitors are placed in the empty spaces of the second layout. In the example of a row-oriented cell structure, the empty spaces may be uniformly distributed along each row for the initial layout. An adjoint sensitivity analysis is performed of the sensitivity of a noise function of the integrated circuit with respect to sizes of the empty spaces between adjacent cells, and an original noise waveform is convolved with an adjoint noise waveform. The convolution may use piecewise linear compressions of the original and adjoint noise waveforms.

Abstract: A method for determining full chip leakage power first estimates leakage power and dynamic power for each circuit macro. The power supply voltage to each macro is first assumed to be nominal. The power dissipation for each macro is modeled as a current source whose value is the estimated power divided by the nominal power supply voltage. The power distribution network is modeled as a resistive grids. The thermal environment of the IC and its electronic package are modeled as multi dimensional grids of thermal elements. Algebraic multi-grid (AMG) methods are used to calculate updated circuit macro voltages and temperatures. The macro voltages and temperatures are updated and updated leakage and dynamic power dissipation are calculated. Iterations are continued until leakage power converges to a final value.

Abstract: A method and system for reducing noise in a power grid of an integrated circuit, which optimizes the placement and sizing of decoupling capacitors in the power grid. Logic cells are located in a first layout of the integrated circuit with empty spaces between the adjacent cells, and the placement of the cells is changed to a second layout wherein the size of the empty spaces between the adjacent cells also change. The decoupling capacitors are placed in the empty spaces of the second layout. In the example of a row-oriented cell structure, the empty spaces may be uniformly distributed along each row for the initial layout. An adjoint sensitivity analysis is performed of the sensitivity of a noise function of the integrated circuit with respect to sizes of the empty spaces between adjacent cells, and an original noise waveform is convolved with an adjoint noise waveform. The convolution may use piecewise linear compressions of the original and adjoint noise waveforms.