Abstract: A computerized simulation validating method for a full-scale distribution network single phase-to-ground fault test is implemented by simulating a full-scale test system with external quantities being controlled to be conformant and validating the full-scale distribution network single phase-to-ground fault test based on a conformance check result between the internal quantities of the field testing and the internal quantities of the simulation testing. The simulation validating method for a full-scale distribution network single phase-to-ground fault test improves normalization and conformance of the full-scale distribution network ground fault test. The computerized simulation validating system, apparatus, and medium for a full-scale distribution network single phase-to-ground fault test also achieve the benefits noted above.

Abstract: Embodiments herein relate to a photonic integrated circuit (PIC). The PIC may include a transmit module and a receive module. An optical port of the PIC may be coupled to the transmit module or the receive module. A semiconductor optical amplifier (SOA) may be positioned in a signal pathway between the optical port and the transmit module or the receive module. Other embodiments may be described and/or claimed.

Abstract: Disclosed herein is a method of making an optical device, such as a photo diode or vertical cavity surface emitting laser (VCSEL). The method entails forming an active device within a substrate, forming a layer of surfactant over the active device; injecting microlens material over the surfactant layer directly above the active device, and curing the injected microlens material to form a microlens over the surfactant layer above the active device, such that the active device is capable of receiving or transmitting an optical signal by way of the microlens. An inkjet printing device may be used to inject the microlens material over the active device.

Abstract: The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness.

Abstract: The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness.