Patents by Inventor Haijiao QIAN

Haijiao QIAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10923597
    Abstract: A transistor and a method for manufacturing the same, a display substrate, and a display apparatus are provided. The transistor may include: a substrate; an active region on the substrate and including a polycrystalline silicon region; an etch stop layer at a side of the polycrystalline silicon region distal to the substrate; and a first heavily doped amorphous silicon region and a second heavily doped amorphous silicon region both at a side of the etch stop layer distal to the substrate; the polycrystalline silicon region having a first side surface corresponding to the first heavily doped amorphous silicon region and a second side surface corresponding to the second heavily doped amorphous silicon region; wherein an orthographic projection of the polycrystalline silicon region on a plane in which a lower surface of the etch stop layer lies does not go beyond the lower surface of the etch stop layer.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: February 16, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Haijiao Qian, Chengshao Yang, Yinhu Huang, Yunhai Wan
  • Publication number: 20200335523
    Abstract: An array substrate, a manufacturing method thereof, and a display panel are provided. The array substrate comprises a base substrate, a plurality of gate lines and gate electrodes on the base substrate, each gate electrode being corresponding to and separate from a respective gate line, a gate insulating layer over the gate electrode and the gate line, the gate insulating layer having a first via hole and a second via hole, the first via hole exposing the gate electrode, the second via hole exposing the gate line, a conductive connection layer and a polysilicon semiconductor layer on the gate insulating layer, the conductive connection layer filling the first via hole and the second via hole to connect the gate line with the gate electrode.
    Type: Application
    Filed: March 12, 2018
    Publication date: October 22, 2020
    Inventors: Binbin Cao, Yinhu HUANG, Chengshao YANG, Haijiao QIAN
  • Patent number: 10700107
    Abstract: It is provided a low-temperature polysilicon thin film transistor formed on a substrate, including: a gate electrode on the substrate; an active layer on the gate electrode, the active layer including a channel region, the channel region having a polysilicon region and amorphous silicon regions respectively on both sides of the polysilicon region; and an etch stop layer on the active layer. An orthogonal projection of the polysilicon region on the substrate is located within an orthogonal projection of the gate electrode on the substrate, and an area of the orthogonal projection the polysilicon region on the substrate is smaller than an area of the orthogonal projection of the gate electrode on the substrate. The orthogonal projection of the polysilicon region on the substrate is located within an orthogonal projection of the etch stop layer on the substrate.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: June 30, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaolong He, Zhifu Li, Guangcai Yuan, Haijiao Qian, Dongsheng Li
  • Publication number: 20200135931
    Abstract: A transistor and a method for manufacturing the same, a display substrate, and a display apparatus are provided. The transistor may include: a substrate; an active region on the substrate and including a polycrystalline silicon region; an etch stop layer at a side of the polycrystalline silicon region distal to the substrate; and a first heavily doped amorphous silicon region and a second heavily doped amorphous silicon region both at a side of the etch stop layer distal to the substrate; the polycrystalline silicon region having a first side surface corresponding to the first heavily doped amorphous silicon region and a second side surface corresponding to the second heavily doped amorphous silicon region; wherein an orthographic projection of the polycrystalline silicon region on a plane in which a lower surface of the etch stop layer lies does not go beyond the lower surface of the etch stop layer.
    Type: Application
    Filed: May 31, 2019
    Publication date: April 30, 2020
    Inventors: Haijiao QIAN, Chengshao YANG, Yinhu HUANG, Yunhai WAN
  • Patent number: 10535781
    Abstract: The disclosure provides a thin film transistor and a fabricating method thereof, and an array substrate. The thin film transistor includes a gate, a first active layer, a second active layer, a first source, a first drain, a second source and a second drain which are provided above a base substrate. The first active layer is located at a side of the gate facing the base substrate, and the second active layer is located at a side of the gate facing away from the first active layer. The first source and the first drain are located at a side of the first active layer facing away from the gate and are connected with the first active layer. The second source and the second drain are located at a side of the second active layer facing away from the gate and are connected with the second active layer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: January 14, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Lin Chen, Haijiao Qian, Chengshao Yang, Mengyu Luan
  • Publication number: 20190259879
    Abstract: It is provided a low-temperature polysilicon thin film transistor formed on a substrate, including: a gate electrode on the substrate; an active layer on the gate electrode, the active layer including a channel region, the channel region having a polysilicon region and amorphous silicon regions respectively on both sides of the polysilicon region; and an etch stop layer on the active layer. An orthogonal projection of the polysilicon region on the substrate is located within an orthogonal projection of the gate electrode on the substrate, and an area of the orthogonal projection the polysilicon region on the substrate is smaller than an area of the orthogonal projection of the gate electrode on the substrate. The orthogonal projection of the polysilicon region on the substrate is located within an orthogonal projection of the etch stop layer on the substrate.
    Type: Application
    Filed: October 27, 2017
    Publication date: August 22, 2019
    Inventors: Xiaolong He, Zhifu Li, Guangcai Yuan, Haijiao Qian, Dongsheng Li
  • Publication number: 20190172932
    Abstract: The present disclosure provides a manufacturing method of thin film transistor, a thin film transistor and a display substrate. The manufacturing method comprises sequentially forming a polysilicon pattern layer and a protective pattern layer on a substrate; etching the protective pattern layer with a first etching gas, so as to obtain a protective pattern; simultaneously etching the protective pattern and the polysilicon pattern layer with a second etching gas by using the protective pattern as a mask, so as to obtain a polysilicon pattern and a residual protective pattern, the protective pattern being etched with the second etching gas at a rate no less than that for etching the polysilicon pattern layer; and forming an amorphous silicon pattern, which is in contact with etched sides of the polysilicon pattern, exposes a part of the residual protective pattern, and forms an active layer together with the polysilicon pattern.
    Type: Application
    Filed: February 1, 2018
    Publication date: June 6, 2019
    Applicants: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Haijiao QIAN, Binbin CAO, Chengshao YANG, Yinhu HUANG
  • Publication number: 20190131461
    Abstract: The disclosure provides a thin film transistor and a fabricating method thereof, and an array substrate. The thin film transistor includes a gate, a first active layer, a second active layer, a first source, a first drain, a second source and a second drain which are provided above a base substrate. The first active layer is located at a side of the gate facing the base substrate, and the second active layer is located at a side of the gate facing away from the first active layer. The first source and the first drain are located at a side of the first active layer facing away from the gate and are connected with the first active layer. The second source and the second drain are located at a side of the second active layer facing away from the gate and are connected with the second active layer.
    Type: Application
    Filed: May 24, 2018
    Publication date: May 2, 2019
    Inventors: Lin CHEN, Haijiao QIAN, Chengshao YANG, Mengyu LUAN