Abstract: Disclosed is a display substrate including a base substrate (10) and a gate drive circuit disposed on the base substrate (10), wherein the gate drive circuit includes a plurality of shift register circuits (GOA) cascaded, a shift register circuit (GOA) includes a plurality of NOT gate circuits, a NOT gate circuit includes a first control transistor and a second control transistor, and transistor types of the first control transistor and the second control transistor are different. Arrangement modes of transistors of at least two NOT gate circuits among the plurality of NOT gate circuits of the shift register circuit (GOA) are different.

Abstract: A display substrate and a display device are provided. The display substrate includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. Each sub-pixel includes a light-emitting region. Sides of each light-emitting region or extension lines of the sides are sequentially connected to form a polygon. Vertexes of the polygon of at least a part of the sub-pixels have non-overlapped regions with angle portions of the corresponding light-emitting regions. Corners of the light-emitting region of at least one sub-pixel at least include a first angle portion. An area of a non-overlapped region between the first angle portion and a vertex angle of the polygon corresponding to the first angle portion is greater than an area of a non-overlapped region between each angle portion among at least part of remaining angle portions and a vertex angle of the polygon corresponding to the each angle portion.

Abstract: Disclosed are a display substrate and a drive method therefor, and a display apparatus. The display substrate includes a plurality of circuit units, and at least one circuit unit includes, at least, a pixel drive circuit and a light emitting signal line. In at least one circuit unit, a pixel drive circuit includes at least a third transistor, a fifth transistor, and a sixth transistor, a second electrode of the fifth transistor is connected with a first electrode of the third transistor, and a first electrode of the sixth transistor is connected with a second electrode of the third transistor. In at least one pixel drive circuit of at least one unit row, a fifth transistor is connected with a light emitting signal line in a previous unit row, and a sixth transistor is connected with a light emitting signal line in a current unit row.

Abstract: A display substrate and a display device are provided. The display substrate includes a pixel driving circuit, the pixel driving circuit includes a first storage capacitor, a second storage capacitor, at least one shield electrode, and at least one double-gate structured transistor; the first storage capacitor at least includes a first electrode plate (71) and a third electrode plate (73), and an orthographic projection of the first electrode plate (71) on the base substrate at least partially overlaps with an orthographic projection of the third electrode plate (73) on the base substrate; the second storage capacitor at least includes a second electrode plate (72) and a fourth electrode plate (74), and an orthographic projection of the second electrode plate (72) on the base substrate at least partially overlaps with an orthographic projection of the fourth electrode plate (74) on the base substrate.

Abstract: A driving circuit includes a first output node control circuit, an output reset circuit, a second output node control circuit, an output circuit, a first energy storage circuit, a second energy storage circuit, and a driving signal output terminal; the output reset circuit controls to connect the driving signal output terminal and the first voltage line under the control of the potential of the first output node; the output circuit controls to connect the driving signal output terminal and the second voltage line under the control of the potential of the second output node; the first energy storage circuit is electrically connected to the first output node and the driving signal output terminal respectively, and the second energy storage circuit is electrically connected to the second output node and the second voltage line respectively, and the first/second energy storage circuit are configured to store electric energy.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes: a base substrate, a first active layer on a side of the base substrate, and a third conductive layer on a side of the first active layer away from the base substrate. The first active layer includes active portions spaced apart, wherein each active portion includes a sub-active portion and a via-hole connection portion connected to each other, and the sub-active portion is disposed corresponding to a transistor of two or more transistors, and configured to form a channel region of the corresponding transistor. The third conductive layer includes at least one bridge portion, wherein the at least one bridge portion is connected to via-hole connection portions in different active portions through via holes, respectively. A sheet resistance of the third conductive layer is less than a sheet resistance of the via hole connection portion.

Abstract: A display substrate includes multiple circuit units, a first power supply connection line, a second power supply connection line, a first power supply line, and a second power supply line, a circuit unit includes a pixel drive circuit, the first power supply line is connected to the pixel drive circuit, and is connected to the first power supply connection line, and the second power supply line is connected to the second power supply connection line; the pixel drive circuit includes a first shielding electrode and at least one transistor with a double-gate structure, an orthographic projection of the first shielding electrode on the base substrate is at least partially overlapped with that of a node between two gate electrodes of a transistor with the double-gate structure on the base substrate; the first shielding electrode is connected to a first power supply connection line or a second power supply connection line.

Abstract: Disclosed are a display substrate and a manufacturing method therefor, and a display apparatus. The display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes a pixel drive circuit and a plurality of scan signal lines connected to the pixel drive circuit, the pixel drive circuit at least includes a plurality of transistors; in the direction perpendicular to the display substrate, the display substrate at least includes a first gate metal layer (GATE 1) arranged on the substrate (101) and a first source drain metal layer (SD1) arranged on a side of the first gate metal layer (GATE 1) away from the substrate (101), a gate electrode of at least one transistor is arranged in the first gate metal layer (GATE 1).

Abstract: A driving circuit, a driving method, a display panel, and a display device are provided. The driving circuit includes: a strobe circuit, wherein the strobe circuit is electrically connected to the strobe control line, a data output terminal of a source driver, and a scanning line, and is configured to control, under control of a strobe control signal provided by the strobe control line, the data output terminal to be connected to or disconnected from the scanning line.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate, and a plurality of sub-pixels, a plurality of first scanning lines, a plurality of second scanning lines and a plurality of data lines arranged on the base substrate. Each sub-pixel includes a sub-pixel driving circuitry, and the sub-pixel driving circuitry includes a driving transistor, a capacitor structure, a compensation transistor and a data write-in transistor.

Abstract: A display panel includes a pixel driving circuit including a first type transistor and a second type transistor, the display panel further includes a base substrate, a first active layer located on a side of the base substrate, a second active layer located on the side of the first active layer away from the base substrate, a first conductive layer located between the first active layer and the second active layer; at least partial structure of the first active layer is used to form a channel region of the first type transistor; at least partial structure of the second active layer is used to form the channel region of the second type transistor; partial structure of the first conductive layer is used to form the gate of the first type transistor, partial structure of the first conductive layer is used to form the bottom gate of the second type transistor.

Abstract: Disclosed is a display substrate including a display region (100) and a bonding region (200) located on a side of the display region (100). The display region (100) includes a base substrate (101) and a drive circuit layer disposed on the base substrate (101). The drive circuit layer includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines (60), and a plurality of data connection lines (70). The data connection lines (70) include a first connection line (71) extending along a first direction and a second connection line (72) extending along a second direction. The first connection line (71) is electrically connected with the second connection line (72) and a data signal line (60) respectively. The first connection line (71) and the second connection line (72) are located in different conductive layers.

Abstract: The disclosure provides a shift register unit, a drive control circuit, a display apparatus, and a drive method. The shift register unit includes: an input circuit coupled to a first node and configured to provide a signal of an input signal terminal to the first node in response to a signal of a first clock signal terminal; a control circuit coupled to the first node, a second node, a control signal terminal, and a first reference signal terminal and configured to provide the signal of the first clock signal terminal and a signal of the first reference signal terminal to a third node and the second node, respectively, in response to a signal of the first node, where the first node is not controlled by the second node or the third node; and an output circuit coupled to the first node and the second node.

Abstract: A display apparatus includes a plurality of first touch channels, second touch channels, first touch traces, second touch traces, and a first touch chip and second touch chip. At least one first touch channel and second touch channel are arranged in each sub-region, and the at least one first touch channel and second touch channel are arranged crosswise and insulated from each other; first touch channels located in different sub-regions are insulated from each other, and second touch channels located in different sub-regions are insulated from each other. In any two sub-regions, first touch traces connected to first touch channels and second touch traces connected to second touch channels are connected to the first touch chip; in remaining two sub-regions except the any two sub-regions, first touch traces connected to first touch channels and second touch traces connected to second touch channels are connected to the second touch chip.

Abstract: A display panel, including an active area and a peripheral area, which is located outside of the active area, wherein the active area comprises a base substrate, and a display structure layer and a touch structure layer sequentially arranged on the base substrate; the peripheral area includes an isolation dam, a first ground trace and a second ground trace arranged on the base substrate; and the first ground trace is located at a side of the isolation dam close to the active area, and the second ground trace is located at a side of the isolation dam away from the active area.

Abstract: A display substrate, a driving method thereof, and a display apparatus. The display substrate includes multiple circuit units. A circuit unit at least includes a pixel drive circuit, and at least one control signal line (24, 25) configured to provide a control signal to the pixel drive circuit. In at least one circuit unit, the pixel drive circuit at least includes a drive transistor (T3), a first control transistor (T5, T8) and a second control transistor (T6, T7), the first control transistor (T5, T8) and second control transistor (T6, T7) are connected to the drive transistor (T3), respectively; in at least one pixel drive circuit of at least one unit row, the first control transistor (T5, T8) is connected to a control signal line (24, 25) in a previous unit row, the second control transistor (T6, T7) is connected to control signal line (24, 25) in the current unit row.

Abstract: Disclosed are a shift register unit, a drive control circuit, a display apparatus and a drive method. The shift register unit includes an input circuit configured to provide a signal from the signal input terminal to the first node in response to a signal from the first clock signal terminal; a first stabilizer circuit, configured to provide a signal from a stability control signal terminal to the first node in response to a signal from a switch control signal terminal; a conducting control circuit configured to establish a conducting path between the first node and the second node in response to a signal from a first reference signal terminal; and an output circuit configured to provide a signal from the second clock signal terminal to the signal output terminal in response to a signal at the second node.

Abstract: A pixel arrangement structure includes: first sub-pixels, second sub-pixels and third sub-pixels, being not overlapped but being spaced apart. The third sub-pixel includes a first edge facing the first sub-pixel, the first sub-pixel includes a second edge facing the third sub-pixel, the third sub-pixel includes a third edge facing the second sub-pixel, and the second sub-pixel includes a fourth edge facing the third sub-pixel, and shapes of the first sub-pixel and the second sub-pixel are circles, the first edge and the second edge are curved edges with a same curvature, the third edge and the fourth edge are curved edges with a same curvature; or shapes of the first sub-pixel and the second sub-pixel are octagons, at least part of the first edge is parallel to at least part of the second edge, at least part of the third edge is parallel to at least part of the fourth edge.

Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, a voltage control circuit and an output circuit; the driving signal generation circuit generates the Nth stage of driving signal; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the output control circuit connects the first control node and the second node under the control of a potential of the first node; the voltage control circuit controls a potential of the second node according to the potential of the first node; the output circuit connects the output driving terminal and the first voltage terminal under the control of the potential of the second node, and connects the output driving terminal and the second voltage terminal under the control of the potential of the second control node; N is a positive integer.

Abstract: A pixel arrangement structure and a display device. The pixel arrangement structure includes at least one array unit, which includes a first pixel row, a second pixel row, a third pixel row and a fourth pixel row; the first pixel row includes a plurality of first sub-pixels; the second pixel row includes a plurality of second sub-pixels and a plurality of third sub-pixels; the third pixel row includes a plurality of first sub-pixels; the fourth pixel row includes a plurality of second sub-pixels and a plurality of third sub-pixels, the first pixel row, the second pixel row, the third pixel row and the fourth pixel row are arranged along a second direction, and a virtual isosceles trapezoid is formed by lines sequentially connecting centers of two adjacent first sub-pixels in the first pixel row and centers of two adjacent first sub-pixels in the third pixel row.