Abstract: A circuit for post-binding testing of a 2.5D chiplet includes an interposer-dedicated TAP controller, an interposer test interface circuit and a chiplet test output control circuit. A chiplet test configuration register and its corresponding instructions are newly added for the interposer-dedicated TAP controller. The interposer test interface circuit uses an output control signal of the chiplet test configuration register to select the opening or closing of a test signal channel between an interposer and a chiplet. The chiplet test output control circuit uses the chiplet test configuration register to output a control signal for control of a test data output of the chiplet on the interposer.

Abstract: A reconfigurable MBIST method based on an adaptive March algorithm is provided. The reconfigurable MBIST method automatically reconfigures different algorithm circuits according to external environment and user instructions to satisfy detection requirements for different faults. The provided adaptive March algorithm is capable of adaptively reorganizing algorithms with different complexities, such that dynamic adjustments can be executed between time complexities of the algorithm and fault coverage rates to achieve a good balance, and the static fault coverage rates are high, thereby effectively improving dynamic fault coverage rates.

Abstract: The present invention relates a packaging structure including: a carrier board and a cementing layer on the surface of the carrier board; chips and passive devices having functional side thereof attached to the cementing layer; and a sealing material layer for packaging and curing, the sealing material being formed on the carrier board on the side attached to the chips and the passive devices. The present invention integrates chips and passive devices and then packages the chips and the passive devices together, and is therefore a packaged product having not single-chip functionality but integrated-system functionality. The present invention is highly integrated, reduces interfering factors such as system-internal electric resistance and inductance, and accommodates growing demand for lighter, thinner, shorter, and smaller semiconductor packaging.

Abstract: A chip packaging structure and packaging method. The packaging structure comprises: a semiconductor substrate; a metal pad provided inside the semiconductor substrate; an insulating layer provided on the semiconductor substrate, the insulating layer having an opening for exposing the metal pad; a sub-ball metal electrode provided on the metal pad; a solder ball provided on the surface of the sub-ball metal electrode, the solder ball having a first apron structure and the first apron structure covering partial metal pad on the periphery of the bottom of the under-ball metal electrode. The chip packaging structure of the present invention enhances the adhesion between the solder ball and the metal pad, and improves the reliability in chip packaging.

Abstract: A chip packaging structure and packaging method. The packaging structure comprises: a semiconductor substrate; a metal pad provided inside the semiconductor substrate; an insulating layer provided on the semiconductor substrate, the insulating layer having an opening for exposing the metal pad; a sub-ball metal electrode provided on the metal pad; a solder ball provided on the surface of the sub-ball metal electrode, the solder ball having a first apron structure and the first apron structure covering partial metal pad on the periphery of the bottom of the under-ball metal electrode. The chip packaging structure of the present invention enhances the adhesion between the solder ball and the metal pad, and improves the reliability in chip packaging.

Abstract: The present invention relates a packaging structure including: a carrier board and a cementing layer on the surface of the carrier board; chips and passive devices having functional side thereof attached to the cementing layer; and a sealing material layer for packaging and curing, the sealing material being formed on the carrier board on the side attached to the chips and the passive devices. The present invention integrates chips and passive devices and then packages the chips and the passive devices together, and is therefore a packaged product having not single-chip functionality but integrated-system functionality. The present invention is highly integrated, reduces interfering factors such as system-internal electric resistance and inductance, and accommodates growing demand for lighter, thinner, shorter, and smaller semiconductor packaging.