Patents by Inventor Hailian LIANG

Hailian LIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11069675
    Abstract: An ESD protection device for bidirectional diode string triggering SCR structure belongs to the field of electro-static discharge of an integrated circuit. A deep N well is arranged on a P substrate, and a first P well, a first N well, a second P well and a second N well are successively arranged from left to right on a surface region of the deep N well. In a second N well region, a mask preparing plate is used to insert the P wells at intervals. The circumference of each P well is isolated by the N well. Each P well is respectively provided with a pair of P+ implantation region and N+ implantation region. The metal wire is connected with the implantation region, and a positive electrode and a negative electrode are led out from the metal wire for forward conduction and reverse conduction.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 20, 2021
    Assignee: JIANGNAN UNIVERSITY
    Inventors: Hailian Liang, Qiang Xu, Xiaofeng Gu
  • Publication number: 20200091138
    Abstract: An ESD protection device for bidirectional diode string triggering SCR structure belongs to the field of electro-static discharge of an integrated circuit. A deep N well is arranged on a P substrate, and a first P well, a first N well, a second P well and a second N well are successively arranged from left to right on a surface region of the deep N well. In a second N well region, a mask preparing plate is used to insert the P wells at intervals. The circumference of each P well is isolated by the N well. Each P well is respectively provided with a pair of P+ implantation region and N+ implantation region. The metal wire is connected with the implantation region, and a positive electrode and a negative electrode are led out from the metal wire for forward conduction and reverse conduction.
    Type: Application
    Filed: May 17, 2018
    Publication date: March 19, 2020
    Inventors: Hailian LIANG, Qiang XU, Xiaofeng GU
  • Patent number: 10290627
    Abstract: The present invention provides an embedded high voltage LDMOS-SCR device with strong voltage clamp and ESD robustness, which can be used as the on-chip ESD protection for high voltage IC. Wherein said the device comprises a P substrate, a P well, a N well, a first field oxide isolation region, a first P+ injection region, a second field oxide isolation region, a first N+ injection region, a first fin polysilicon gate, a second N+ injection region, a second fin polysilicon gate, a third N+ injection region, a third fin polysilicon gate, a polysilicon gate, a fourth fin polysilicon gate, a second P+ injection region, a fifth fin polysilicon gate, a third P+ injection region, a sixth fin polysilicon gate, a fourth P+ injection region, a third oxygen isolation region, a fourth N+ injection region and a fourth field oxygen isolation region.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: May 14, 2019
    Assignee: JIANGNAN UNIVERSITY
    Inventors: Hailian Liang, Huyun Liu, Xiaofeng Gu, Sheng Ding
  • Publication number: 20190006344
    Abstract: The present invention provides an embedded high voltage LDMOS-SCR device with strong voltage clamp and ESD robustness, which can be used as the on-chip ESD protection for high voltage IC. Wherein said the device comprises a P substrate, a P well, a N well, a first field oxide isolation region, a first P+ injection region, a second field oxide isolation region, a first N+ injection region, a first fin polysilicon gate, a second N+ injection region, a second fin polysilicon gate, a third N+ injection region, a third fin polysilicon gate, a polysilicon gate, a fourth fin polysilicon gate, a second P+ injection region, a fifth fin polysilicon gate, a third P+ injection region, a sixth fin polysilicon gate, a fourth P+ injection region, a third oxygen isolation region, a fourth N+ injection region and a fourth field oxygen isolation region.
    Type: Application
    Filed: March 11, 2016
    Publication date: January 3, 2019
    Inventors: Hailian LIANG, Huyun LIU, Xiaofeng GU, Sheng DING