Patents by Inventor Hailiang CUI

Hailiang CUI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • IO interface level shift circuit, IO interface level shift method and storage medium
    Patent number: 10200042
    Abstract: Provided is an IO interface level shift circuit, comprising: an intermediate level generation circuit (11) and a level shift circuit (12). The intermediate level generation circuit is configured to provide an intermediate level Vdd_io of an IO interface. The level shift circuit is configured to convert an external logical signal into a signal in an internal power domain of a chip according to the intermediate level Vdd_io of the IO interface. Also provided are an IO interface level shift method and a storage medium. The interface level shift circuit enables level shift on an external IO signal at any level in a voltage withstanding domain of a device without adding a power domain suitable for an external IO level in the circuit.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: February 5, 2019
    Assignee: Sanechips Technology Co. Ltd.
    Inventor: Hailiang Cui
  • IO INTERFACE LEVEL SHIFT CIRCUIT, IO INTERFACE LEVEL SHIFT METHOD AND STORAGE MEDIUM
    Publication number: 20170222650
    Abstract: Provided is an IO interface level shift circuit, comprising: an intermediate level generation circuit (11) and a level shift circuit (12). The intermediate level generation circuit is configured to provide an intermediate level Vdd_io of an IO interface. The level shift circuit is configured to convert an external logical signal into a signal in an internal power domain of a chip according to the intermediate level Vdd_io of the IO interface. Also provided are an IO interface level shift method and a storage medium. The interface level shift circuit enables level shift on an external IO signal at any level in a voltage withstanding domain of a device without adding a power domain suitable for an external IO level in the circuit.
    Type: Application
    Filed: April 14, 2014
    Publication date: August 3, 2017
    Inventor: Hailiang CUI