Patents by Inventor Hailin Zhao
Hailin Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11889133Abstract: The present disclosure describes techniques of processing burst traffic. In the present application, when a service request is received, it is determined whether there is service data corresponding to the service request in a buffer unit. If so, the corresponding service data in the buffer unit is directly sent to a client computer so as to reduce access pressure of a second service layer; if not, determining whether a request frequency associated with the service request is greater than a frequency threshold; when the request frequency of the service request is greater than the frequency threshold, it indicates that the second service layer of the service type corresponding to the service request reaches the upper limit of capacity. In this case, the service request is sent to a first service layer so as to acquire corresponding service data.Type: GrantFiled: April 16, 2020Date of Patent: January 30, 2024Assignee: SHANGHAI HODE INFORMATION TECHNOLOGY CO., LTD.Inventor: Hailin Zhao
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Patent number: 11862595Abstract: The present disclosure provides a packaging method for a fan-out wafer-level packaging structure, including: providing two or more semiconductor chips, and bonding the semiconductor chips to a bonding layer; packaging the semiconductor chips by a plastic packaging layer; removing the bonding layer, and forming a redistribution layer on the semiconductor chips, so as to achieve interconnection between the semiconductor chips, where the redistribution layer includes one or more redistribution sublayers stacked in sequence, and a method for forming each redistribution sublayer includes: forming a dielectric layer on the semiconductor chips; forming vias in the dielectric layer by photolithography; baking the dielectric layer having the vias formed therein, wherein the warpage of the dielectric layer around the vias is mitigated; curing the dielectric layer; and forming on the dielectric layer a patterned metal distribution layer corresponding to the vias; and forming metal bumps on the redistribution layer.Type: GrantFiled: September 8, 2021Date of Patent: January 2, 2024Assignee: SJ SEMICONDUCTOR(JIANGYIN) CORPORATIONInventor: Hailin Zhao
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Patent number: 11652085Abstract: The present disclosure provides a fan-out wafer-level packaging structure and a method for packaging the same. The structure includes: two or more semiconductor chips with a bonding pad, the semiconductor chips are arranged in a fan-out wafer array, and each of the semiconductor chips has an initial position, respectively; a plastic packaging layer, covering surfaces of the semiconductor chips and between the semiconductor chips, each of the semiconductor chips has an offset position, respectively, and the offset position has an offset distance relative to the initial position; a redistribution layer formed on the semiconductor chips, to realize interconnection between the semiconductor chips, the redistribution layer includes at least one first redistribution layer, the first redistribution layer is formed on a surface of the semiconductor chips and is aligned and in contact with the bonding pad of the semiconductor chips; and a metal bump formed on the redistribution layer.Type: GrantFiled: June 1, 2022Date of Patent: May 16, 2023Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATIONInventor: Hailin Zhao
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Publication number: 20220293559Abstract: The present disclosure provides a fan-out wafer-level packaging structure and a method for packaging the same. The structure includes: two or more semiconductor chips with a bonding pad, the semiconductor chips are arranged in a fan-out wafer array, and each of the semiconductor chips has an initial position, respectively; a plastic packaging layer, covering surfaces of the semiconductor chips and between the semiconductor chips, each of the semiconductor chips has an offset position, respectively, and the offset position has an offset distance relative to the initial position; a redistribution layer formed on the semiconductor chips, to realize interconnection between the semiconductor chips, the redistribution layer includes at least one first redistribution layer, the first redistribution layer is formed on a surface of the semiconductor chips and is aligned and in contact with the bonding pad of the semiconductor chips; and a metal bump formed on the redistribution layer.Type: ApplicationFiled: June 1, 2022Publication date: September 15, 2022Inventor: Hailin Zhao
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Publication number: 20220272392Abstract: The present disclosure describes techniques of processing burst traffic. In the present application, when a service request is received, it is determined whether there is service data corresponding to the service request in a buffer unit. If so, the corresponding service data in the buffer unit is directly sent to a client computer so as to reduce access pressure of a second service layer; if not, determining whether a request frequency associated with the service request is greater than a frequency threshold; when the request frequency of the service request is greater than the frequency threshold, it indicates that the second service layer of the service type corresponding to the service request reaches the upper limit of capacity. In this case, the service request is sent to a first service layer so as to acquire corresponding service data.Type: ApplicationFiled: April 16, 2020Publication date: August 25, 2022Inventor: Hailin ZHAO
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Patent number: 11380649Abstract: The present disclosure provides a fan-out wafer-level packaging structure and a method for packaging the same. The structure includes: two or more semiconductor chips with a bonding pad, the semiconductor chips are arranged in a fan-out wafer array, and each of the semiconductor chips has an initial position, respectively; a plastic packaging layer, covering surfaces of the semiconductor chips and between the semiconductor chips, each of the semiconductor chips has an offset position, respectively, and the offset position has an offset distance relative to the initial position; a redistribution layer formed on the semiconductor chips, to realize interconnection between the semiconductor chips, the redistribution layer includes at least one first redistribution layer, the first redistribution layer is formed on a surface of the semiconductor chips and is aligned and in contact with the bonding pad of the semiconductor chips; and a metal bump formed on the redistribution layer.Type: GrantFiled: March 19, 2021Date of Patent: July 5, 2022Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATIONInventor: Hailin Zhao
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Publication number: 20220077096Abstract: The present disclosure provides a packaging method for a fan-out wafer-level packaging structure, including: providing two or more semiconductor chips, and bonding the semiconductor chips to a bonding layer; packaging the semiconductor chips by a plastic packaging layer; removing the bonding layer, and forming a redistribution layer on the semiconductor chips, so as to achieve interconnection between the semiconductor chips, where the redistribution layer includes one or more redistribution sublayers stacked in sequence, and a method for forming each redistribution sublayer includes: forming a dielectric layer on the semiconductor chips; forming vias in the dielectric layer by photolithography; baking the dielectric layer having the vias formed therein, wherein the warpage of the dielectric layer around the vias is mitigated; curing the dielectric layer; and forming on the dielectric layer a patterned metal distribution layer corresponding to the vias; and forming metal bumps on the redistribution layer.Type: ApplicationFiled: September 8, 2021Publication date: March 10, 2022Inventor: Hailin ZHAO
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Publication number: 20220077107Abstract: The present disclosure provides a fan-out wafer-level packaging structure and a method for packaging the same. The structure includes: two or more semiconductor chips with a bonding pad, the semiconductor chips are arranged in a fan-out wafer array, and each of the semiconductor chips has an initial position, respectively; a plastic packaging layer, covering surfaces of the semiconductor chips and between the semiconductor chips, each of the semiconductor chips has an offset position, respectively, and the offset position has an offset distance relative to the initial position; a redistribution layer formed on the semiconductor chips, to realize interconnection between the semiconductor chips, the redistribution layer includes at least one first redistribution layer, the first redistribution layer is formed on a surface of the semiconductor chips and is aligned and in contact with the bonding pad of the semiconductor chips; and a metal bump formed on the redistribution layer.Type: ApplicationFiled: March 19, 2021Publication date: March 10, 2022Inventor: Hailin Zhao
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Publication number: 20200329698Abstract: The invention provides compositions, treatment means and protocols for induction of protective effects of organ grafts by administration of Dexmedetomidine, in combination with/without xenon or argon, in the conventional organ graft preservation solution storage solution. In one particular embodiment, the invention provides the activation of molecular pathways associated with reduction of oxidative stress and inhibition of regulated necrosis.Type: ApplicationFiled: April 19, 2019Publication date: October 22, 2020Applicant: Nobilis Therapeutics, Inc.Inventors: Daqing MA, Hailin ZHAO, Andrew J.T. GEORGE, Qian CHEN, Jiateng GU, Jiaolin NING, Kaizhi LU
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Publication number: 20190185896Abstract: The invention provides compositions, treatment means and protocols for induction of regenerative processes by administration of noble gases. In one particular embodiment the invention provides the stimulation of production of factors associated with augmentation of hematopoiesis, angiogenesis, and wound healing by exposure of cells, organs, or mammals to a noble gas. In a particular embodiment the invention provides the administration of argon as a noble gas capable of upregulating production of VEGF and angiopoietin.Type: ApplicationFiled: December 19, 2017Publication date: June 20, 2019Applicant: NOBILIS THERAPEUTICS, INC.Inventors: Daqing Ma, Hailin Zhao, Kaizhi Lu, Jiaolin Ning, Jianteng Gu, Thomas Ichim, Vlad Bogin