Abstract: To provide a method and device for testing the size and conductivity of a foreign material adhered to a substrate for a liquid crystal display device, there is provided a method of testing whether a foreign material including a metal element is adhered to a substrate for a liquid crystal display device, the method including a first test step of detecting the size and position of the foreign material adhered to the substrate and a next step of testing whether the foreign material includes the metal element at the position detected in the first test step.

Abstract: Quiescent supply current (IDDQ) verification, prediction, and debugging of low power semiconductor devices are enhanced by IDDQ defect diagnosis. If all IDDQ patterns fail verification, per module analysis is performed to sort out potential module design issues or cell constraint issues. For issues of missing constraints, and cell design or implementation issues leading to extra leakage that could be avoided by adding constraints, there are usually IDDQ patterns that correlate with expectations, and patterns that do not, due to the random nature of unconstrained scan cell values as determined by the pattern generation tool. Differentiating good and bad IDDQ patterns can identify root causes of IDDQ issues and additional constraints to fix the bad IDDQ vectors. These verification procedures are achieving IDDQ test success and short time to market, as well as significantly faster time to volume and improved yields because of having a higher quality and better-controlled IDDQ test.

Abstract: Procedures are disclosed to automate constraint and power mode (PM) setup determination for quiescent power supply current (IDDQ) testing of a semiconductor design. Starting with known constraints and PM setup, if available, an estimation is run to obtain minimum, lower bound (LB), expected, upper bound (UB), and maximum IDDQ estimates for individual cells. The estimates are sorted by range (UB-LB), and by elevation (expected-minimum). A constraint is added to control the power of the cell with the highest range. A constraint or a PM entry is added to reduce elevation of the cell with the highest elevation, based on a predetermined property of the cell. With the adjusted constraints and PM setup, the steps are repeated. Iteration continues until (1) the top cells are not custom cells, memories, or macros, or (2) the contributions of the top cells to the design's range and elevation are below predetermined limits.

Abstract: To provide a method and device for testing the size and conductivity of a foreign material adhered to a substrate for a liquid crystal display device, there is provided a method of testing whether a foreign material including a metal element is adhered to a substrate for a liquid crystal display device, the method including a first test step of detecting the size and position of the foreign material adhered to the substrate and a next step of testing whether the foreign material includes the metal element at the position detected in the first test step.

Abstract: To provide a method and device for testing the size and conductivity of a foreign material adhered to a substrate for a liquid crystal display device, there is provided a method of testing whether a foreign material including a metal element is adhered to a substrate for a liquid crystal display device, the method including a first test step of detecting the size and position of the foreign material adhered to the substrate and a second test step of testing whether the foreign material includes the metal element at the position detected in the first test step.

Abstract: Quiescent supply current (IDDQ) verification, prediction, and debugging of low power semiconductor devices are enhanced by IDDQ defect diagnosis. If all IDDQ patterns fail verification, per module analysis is performed to sort out potential module design issues or cell constraint issues. For issues of missing constraints, and cell design or implementation issues leading to extra leakage that could be avoided by adding constraints, there are usually IDDQ patterns that correlate with expectations, and patterns that do not, due to the random nature of unconstrained scan cell values as determined by the pattern generation tool. Differentiating good and bad IDDQ patterns can identify root causes of IDDQ issues and additional constraints to fix the bad IDDQ vectors. These verification procedures are achieving IDDQ test success and short time to market, as well as significantly faster time to volume and improved yields because of having a higher quality and better-controlled IDDQ test.