Patents by Inventor Hailong Yu
Hailong Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240321997Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes: providing a substrate, where gate structures are formed on the substrate, source-drain doped regions are formed in the substrate on two sides of each gate structure, and a bottom dielectric layer between adjacent gate structures is formed on the source-drain doped regions; forming liner metal layers in contact with the gate structures on top surfaces of the gate structures, where the liner metal layers are made of a pure metal; forming a top dielectric layer on the bottom dielectric layer to cover the liner metal layers; and forming gate plugs penetrating through the top dielectric layer and in contact with the liner metal layers using a first selective deposition process.Type: ApplicationFiled: July 20, 2021Publication date: September 26, 2024Inventors: Hailong YU, Xuezhen JING, Jinhui MENG
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Publication number: 20240310684Abstract: A display panel and a display apparatus. The display panel includes: a display region and at least one non-display region adjacent to the display region, and a boundary between the at least one non-display region and the display region has a curve part; and the display panel includes: a plurality of pixels, distributed in a first direction and a second direction in an array; the plurality of pixels include: a plurality of first pixel groups adjacent to the curve part, each first pixel group is divided into a plurality of first sub-pixel groups distributed in the first direction, each first sub-pixel group includes at least one first sub-pixel, a width of the first sub-pixel in the first direction is smaller than a width of the first sub-pixel in the second direction.Type: ApplicationFiled: April 29, 2022Publication date: September 19, 2024Inventors: Yabin LIN, Qiaoni WANG, Jianming HUANG, Hailong YU, Xuezhen SU, Wanping PAN, Xiaobo JIA
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Patent number: 12092614Abstract: An ultrasonic-resilience value testing apparatus for an inorganic non-metal plate, including: a fixing mechanism, a testing mechanism and a control mechanism. The fixing mechanism is for carrying and fixing an inorganic non-metal plate to be tested; the testing mechanism is for performing ultrasonic-resilience value testing on the inorganic non-metal plate fixed on the fixing mechanism; and the control mechanism is in communication connection to the fixing mechanism and the testing mechanism, and is for controlling the fixing mechanism and the testing mechanism to run. By setting the fixing mechanism, problems such as slipping, angle deviation, vibration or movement and damage to the test sample are avoided. By setting the testing mechanism for the resilience value testing, the phenomenon that the relevant mechanical properties of the test sample cannot be accurately reflected since a resilience angle, a velocity and the like are affected by human factors, is improved.Type: GrantFiled: March 18, 2020Date of Patent: September 17, 2024Assignees: DONGGUAN CITY WONDERFUL CERAMICS INDUSTRIAL PARK CO., LTD., JIANGXI HEMEI CERAMICS CO., LTD., GUANGDONG JIAMEI CERAMICS CO., LTDInventors: Yuezeng Xie, Jianping Huang, Kehui Lin, Hailong Yu, Zhongmin Li
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Publication number: 20240301795Abstract: The present invention relates to the technical field of disaster model experiment of underground engineering, and more particularly to an experimental system for surrounding rock crack evolution and water inrush disaster change in a tunnel excavation of a near-covered karst cave. The experimental system includes a base, an upper crossbeam, standing columns, an experimental cabin, guide rails, a tunnel excavation device and an experimental control system. By setting a tunnel excavation device instead of the traditional manual excavation experimental system, the step-by-step excavation of the tunnel is realized. A camera inside the tunnel mold collects real-time images of the whole process of tunnel excavation. The front side plate is separated from the whole experimental cabin, such that the deformation and damage of the front side of the physical model can be directly observed.Type: ApplicationFiled: March 6, 2023Publication date: September 12, 2024Inventors: Hailong Wang, Chuanyang Jia, Guibin Zhang, Xiaoyuan Song, Xizhen Sun, Keming Liu, Xianbin Yu, Wei Li
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Patent number: 12085809Abstract: A backlight module includes: a first optical element and a fixing frame arranged around the first optical element. The fixing frame includes a first edge frame and a second edge frame that are oppositely arranged, and a third edge frame and a fourth edge frame that are oppositely arranged. The side of each edge frame of the fixing frame facing the first optical element is provided with a plurality of adhesive tapes that are independent of each other and extend in an extension direction of the each edge frame. The first optical element is fixed to the fixing frame through the adhesive tapes.Type: GrantFiled: October 25, 2021Date of Patent: September 10, 2024Assignees: Fuzhou BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Wanping Pan, Enlong Wu, Changjia Fu, Jianming Huang, Hailong Yu, Yabin Lin, Xuezhen Su, Xiaobo Jia, Chuanhe Jing
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Publication number: 20240294482Abstract: Provided is a method for catalytically activating carbon dioxide as a carbonylation reagent with inorganic sulfur. In the method, carbon dioxide can be used to replace a toxic and harmful carbonylation reagent in the presence of H2S and an alkali for the synthesis of a carbonyl-containing fine chemical product. The method has a relatively high atomic economy and can reduce the generation of by-products.Type: ApplicationFiled: December 20, 2021Publication date: September 5, 2024Inventors: Ning ZHU, Rongting HE, Silliu CHENG, Lili YU, Jiakai WU, Guanghui SHI, Yang WANG, Tingxuan FANG, Hailong HONG, Limin HAN
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Publication number: 20240276502Abstract: A terminal device determines a physical resource block PRB position of a resource corresponding to a physical uplink control channel PUCCH; and the terminal device sends the PUCCH based on the PRB position, wherein the PRB position satisfies RBBWPoffset+?rPUCCH/NCS? or NBWPsize?1?RBBWPoffset??rPUCCH/NCS?, rPUCCH is a PUCCH resource index, NCS is a quantity of cyclic shifts of a common PUCCH resource set, RBBWPoffset is a frequency domain offset value of the common PUCCH resource set, and NBWPSize is a size of a bandwidth part configured with a PUCCH resource.Type: ApplicationFiled: April 19, 2024Publication date: August 15, 2024Inventors: Hailong Hou, Zhanzhan Zhang, Zhe Jin, Zheng Yu, Yi Wang, Ronghui Wen
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Publication number: 20240258238Abstract: A semiconductor structure includes a substrate, a covering layer on the substrate, an auxiliary layer on the covering layer, a first dielectric layer on surfaces of the substrate and the auxiliary layer, and a conductive structure in the first dielectric layer. The semiconductor structure also includes a second dielectric layer on surfaces of the first dielectric layer and the conductive structure, a first opening in the second dielectric layer and the first dielectric layer, and a second opening in the second dielectric layer. The first opening exposes the auxiliary layer, and the second opening exposes the top surface of the conductive structure. A first conductive layer is in the first opening, and a second conductive layer is in the second opening. A growth rate of the first conductive layer over the auxiliary layer is higher than the growth rate of the first conductive layer over the covering layer.Type: ApplicationFiled: May 31, 2021Publication date: August 1, 2024Inventors: Zengsheng XU, Xuezhen JING, Hao ZHANG, Tiantian ZHANG, Hailong YU
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Publication number: 20240203877Abstract: A semiconductor structure and a formation method of the semiconductor structure are provided in the present disclosure. The semiconductor structure includes a substrate, including a first device region and a second device region; a first device layer on the substrate, where a first transistor at the first device region is in the first device layer; a second device layer on the first device layer, where a second transistor at the second device region is in the second device layer, and projections of the first transistor and the second transistor on a surface of the substrate are non-overlapped with each other; and an electrical interconnection structure in the first device layer and the second device layer, where the electrical interconnection structure is electrically connected to each of the first transistor and the second transistor.Type: ApplicationFiled: December 11, 2023Publication date: June 20, 2024Inventors: Bo SU, Hailong YU
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Patent number: 11990415Abstract: A semiconductor device and method for forming same are provided. The method for forming a semiconductor device includes: providing a base; forming an interlayer dielectric layer over the base; forming contact holes by etching the interlayer dielectric layer; forming a barrier layer over the base in the contact holes; and forming a metal layer over the barrier layer. The contact holes exposed a portion of a surface of the base. The metal layer fully filled the contact hole.Type: GrantFiled: August 12, 2020Date of Patent: May 21, 2024Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Tiantian Zhang, Xuezhen Jing, Zheyuan Tong, Zhangru Xiao, Hailong Yu
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Patent number: 11959881Abstract: A non-destructive testing method for flexural strength of fine ceramic, an apparatus, and a storage medium, including adjusting an uncut intact fine ceramic test sample to an ultrasonic testing position, and fixing the test sample; adjusting an ultrasonic testing instrument, controlling and adjusting the positions of ultrasonic testing probes of the ultrasonic testing instrument until the ultrasonic testing probes, the fine ceramic test sample and the resiling direction are located on the same plane, performing ultrasonic testing on the test sample, and collecting ultrasonic testing data of the test sample; adjusting the position of the fine ceramic test sample until a resilience testing rod and the test sample are located on the same plane and fixed, performing resilience testing on the test sample, and collecting resilience testing data of the test sample; and building a data model, or substituting testing data into the pre-built data model.Type: GrantFiled: March 18, 2020Date of Patent: April 16, 2024Assignees: DONGGUAN CITY WONDERFUL CERAMICS INDUSTRIAL PARK CO., LTD., JIANGXI HEMEI CERAMICS CO., LTD., GUANGDONG JIAMEI CERAMICS CO., LTDInventors: Jianping Huang, Yuezeng Xie, Kehui Lin, Hailong Yu
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Publication number: 20240063298Abstract: A semiconductor structure includes a plurality of composite layers formed on a portion of a substrate. An interlayer dielectric layer is formed on the substrate and the plurality of composite layers. A first gate trench is formed on the interlayer dielectric layer, and a gate sidewall is formed on a side surface of the first gate trench. The composite layer includes stacked channel layers and a second gate trench between neighboring channel layers. The first gate trench and the gate sidewall cross over a portion of a sidewall and a portion of a top surface of the composite layer, and the first gate trench communicates with the second gate trench. A gate is formed in the first and second gate trenches. The doping region is formed in a channel layer. The source-drain layer is formed in the composite layer on two sides of the gate structure.Type: ApplicationFiled: August 15, 2023Publication date: February 22, 2024Inventors: Bo SU, Hailong YU, Jing ZHANG, Hansu OH
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Patent number: 11908906Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided. The method includes providing a substrate, forming a first dielectric layer and a plurality of gate structures, forming source-drain doped regions, and forming a source-drain plug. The first dielectric layer covers surfaces of the gate structure, the source-drain doped region and the source-drain plug. The method also includes forming a first plug in the first dielectric layer, and forming a second dielectric layer on the first dielectric layer. The first plug is in contact with a top surface of one of the source-drain plug and the gate structure. The second dielectric layer covers the first plug. Further, the method includes forming a second plug material film in the first and second dielectric layers. The second plug material film is in contact with the top surface of one of the source-drain plug and the gate structure.Type: GrantFiled: August 26, 2021Date of Patent: February 20, 2024Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Hailong Yu, Xuezhen Jing, Hao Zhang, Tiantian Zhang, Jinhui Meng
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Publication number: 20240012289Abstract: A backlight module includes: a first optical element and a fixing frame arranged around the first optical element. The fixing frame includes a first edge frame and a second edge frame that are oppositely arranged, and a third edge frame and a fourth edge frame that are oppositely arranged. The side of each edge frame of the fixing frame facing the first optical element is provided with a plurality of adhesive tapes that are independent of each other and extend in an extension direction of the each edge frame.Type: ApplicationFiled: October 25, 2021Publication date: January 11, 2024Inventors: Wanping PAN, Enlong WU, Changjia FU, Jianming HUANG, Hailong YU, Yabin LIN, Xuezhen SU, Xiaobo JIA, Chuanhe JING
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Patent number: 11867667Abstract: A non-destructive testing method for an elastic modulus of fine ceramic, an apparatus, and a storage medium, including controlling intact fine ceramic to enter a first testing position, fixing the test sample, controlling an ultrasonic testing instrument to be adjusted to a position of the sample, performing ultrasonic testing e, and collecting testing data; adjusting the sample to a second testing position, performing resilience testing on the sample, and collecting resilience data; building a data model according to the testing data, or substituting the testing data into the pre-built data model to obtain elastic modulus characterization data of the test sample. The test sample does not need to be cut into small-size test samples and is not destroyed, and the intact fine ceramic is subjected to non-destructive testing. The accuracy of tested data is improved, damage to the test sample is also avoided, and reuse of the sample is realized.Type: GrantFiled: March 18, 2020Date of Patent: January 9, 2024Assignees: DONGGUAN CITY WONDERFUL CERAMICS INDUSTRIAL PARK CO., LTD., JIANGXI HEMEI CERAMICS CO., LTD., GUANGDONG JIAMEI CERAMICS CO., LTD.Inventors: Jianping Huang, Yuezeng Xie, Kehui Lin, Hailong Yu
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Patent number: 11809649Abstract: An electronic ink screen and a method for manufacturing the same are provided. The electronic ink screen includes: a display module including pixel units configured to display by using electronic ink; and a control module configured to convert a touch signal applied from outside into a change of electric signal of corresponding one or more pixel units through an electrode microstructure, so that a display state of the corresponding one or more pixel units is changed from an initial state; the electrode microstructure includes sub-electrode microstructures, each sub-electrode microstructure includes a first nano electrode and a second nano electrode which are made of different materials, the first nano electrode and the second nano electrode are arranged at intervals and configured to be in mutual friction contact in response to that the touch signal applied from the outside is received, so as to generate charge transferring.Type: GrantFiled: November 29, 2019Date of Patent: November 7, 2023Assignees: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Li Cheng, Jianming Huang, Hailong Yu, Yabin Lin, Chuanhe Jing, Wanping Pan, Xianjuan Jin
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Publication number: 20230330131Abstract: Disclosed herein is an ingestible composition comprising a sphingan and its use as a prebiotic.Type: ApplicationFiled: March 3, 2023Publication date: October 19, 2023Applicant: CP KELCO U.S., INC.Inventors: Neil A. Morrison, Hailong Yu, John P. Abdou, Narayana Murthy Manjunatha, Todd A. Talashek
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Patent number: 11735476Abstract: A semiconductor structure and its fabrication method are provided. The method includes: providing a substrate and a first metal layer in the substrate; forming a dielectric layer with a first opening exposing a portion of a top surface of the first metal layer on the substrate; bombarding the portion of the top surface of the first metal layer exposed by the first opening, by using a first sputtering treatment, to make metal materials on the top surface of the first metal layer be sputtered onto sidewalls of the first opening to form a first adhesion layer; and forming a second metal layer on a surface of the first adhesion layer and on the exposed portion of the top surface of the first metal layer using a first metal selective growth process.Type: GrantFiled: September 15, 2020Date of Patent: August 22, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Hailong Yu, Jingjing Tan, Xuezhen Jing, Wen Guo
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Patent number: 11658067Abstract: A method for forming a semiconductor structure includes providing an initial semiconductor structure formed in a substrate; forming a dielectric layer on the substrate; forming a first opening in the dielectric layer to expose a portion of the initial semiconductor structure; etching the portion of the initial semiconductor structure exposed at a bottom of the first opening to form a second opening in the initial semiconductor structure; and forming a contact layer in the second opening and a third opening in the contact layer. The contact layer has a concave top surface, and the third opening is located above the concave top surface of the contact layer and under the first opening. The method further includes forming a conductive structure in the first opening and the third opening.Type: GrantFiled: August 10, 2020Date of Patent: May 23, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Hailong Yu, Jingjing Tan, Hao Zhang
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Publication number: 20230152913Abstract: An electronic ink screen and a method for manufacturing the same are provided. The electronic ink screen includes: a display module including pixel units configured to display by using electronic ink; and a control module configured to convert a touch signal applied from outside into a change of electric signal of corresponding one or more pixel units through an electrode microstructure, so that a display state of the corresponding one or more pixel units is changed from an initial state; the electrode microstructure includes sub-electrode microstructures, each sub-electrode microstructure includes a first nano electrode and a second nano electrode which are made of different materials, the first nano electrode and the second nano electrode are arranged at intervals and configured to be in mutual friction contact in response to that the touch signal applied from the outside is received, so as to generate charge transferring.Type: ApplicationFiled: November 29, 2019Publication date: May 18, 2023Inventors: Li CHENG, Jianming HUANG, Hailong YU, Yabin LIN, Chuanhe JING, Wanping PAN, Xianjuan JIN